AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 282
![IC ARM7 MCU FLASH 256K 100LQFP](/photos/6/76/67646/313-100-lqfp_sml.jpg)
AT91SAM7A3-AU
Manufacturer Part Number
AT91SAM7A3-AU
Description
IC ARM7 MCU FLASH 256K 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7A3-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
60MHz
Connectivity
CAN, I²C, MMC, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Controller Family/series
AT91SAM7xx
No. Of I/o's
62
Ram Memory Size
32KB
Cpu Speed
60MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
60 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
62
Interface Type
CAN/SPI/I2S/TWI/USART/USB
On-chip Adc
2(8-chx10-bit)
Number Of Timers
3
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Ram Size
32 KB
Maximum Clock Frequency
60 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
Minimum Operating Temperature
- 40 C
Cpu Family
91S
Device Core Size
32b
Frequency (max)
60MHz
Total Internal Ram Size
32KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7A3-AU
Manufacturer:
MXIC
Quantity:
1 001
Company:
Part Number:
AT91SAM7A3-AU
Manufacturer:
Atmel
Quantity:
730
- Current page: 282 of 594
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29.5.3.2
6042E–ATARM–14-Dec-06
Asynchronous Receiver
none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent
first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first.
The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is sup-
ported in asynchronous mode only.
Figure 29-5. Character Transmit
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmit-
ter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter
Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the
characters written in US_THR have been processed. When the current character processing
is completed, the last character written in US_THR is transferred into the Shift Register of the
transmitter and US_THR becomes empty, thus TXRDY raises.
Both TXRDY and TXEMPTY bits are low since the transmitter is disabled. Writing a character
in US_THR while TXRDY is active has no effect and the written character is lost.
Figure 29-6. Transmitter Status
If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver over-
samples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock,
depending on the OVER bit in the Mode Register (US_MR).
The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a
start bit is detected and data, parity and stop bits are successively sampled on the bit rate
clock.
If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data
bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is
Baud Rate
TXEMPTY
Baud Rate
Example: 8-bit, Parity Enabled One Stop
US_THR
TXRDY
Clock
Write
Clock
TXD
TXD
Start
Bit
Start
Bit
D0
D1
D0
D2
D3
D1
D4
D5
D2
D6
D7
AT91SAM7A3 Preliminary
D3
Parity
Bit
Stop
Bit
D4
Start
Bit
D0
D5
D1
D2
D6
D3
D4
D7
D5
D6
Parity
Bit
D7
Parity
Bit
Stop
Bit
Stop
Bit
282
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