AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 499

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

36.6.3
6042E–ATARM–14-Dec-06
Time Management Unit
The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the
bit clock of the CAN bus line. It is enabled when the CAN controller is enabled (CANEN set in
the CAN_MR register). It is automatically cleared in the following cases:
The application can also reset the internal timer by setting TIMRST in the CAN_TCR register.
The current value of the internal timer is always accessible by reading the CAN_TIM register.
When the timer rolls-over from FFFFh to 0000h, TOVF (Timer Overflow) signal in the CAN_SR
register is set. TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register.
Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is gen-
erated while TOVF is set.
In a CAN network, some CAN devices may have a larger counter. In this case, the application
can also decide to freeze the internal counter when the timer reaches FFFFh and to wait for a
restart condition from another device. This feature is enabled by setting TIMFRZ in the
CAN_MR register. The CAN_TIM register is frozen to the FFFFh value. A clear condition
described above restarts the timer. A timer overflow (TOVF) interrupt is triggered.
To monitor the CAN bus activity, the CAN_TIM register is copied to the CAN _TIMESTP regis-
ter after each start of frame or end of frame and a TSTP interrupt is triggered. If TEOF bit in
the CAN_MR register is set, the value is captured at each End Of Frame, else it is captured at
each Start Of Frame. Depending on the corresponding mask in the CAN_IMR register, an
interrupt is generated while TSTP is set in the CAN_SR. TSTP bit is cleared by reading the
CAN_SR register.
The time management unit can operate in one of the two following modes:
Timestamping Mode is enabled by clearing TTM field in the CAN_MR register. Time Triggered
Mode is enabled by setting TTM field in the CAN_MR register.
• after a reset
• when the CAN controller is in Low-power Mode is enabled (LPM bit set in the CAN_MR and
• after a reset of the CAN controller (CANEN bit in the CAN_MR register)
• in Time-triggered Mode, when a message is accepted by the last mailbox (rising edge of
• Timestamping mode: The value of the internal timer is captured at each Start Of Frame or
• Time Triggered mode: A mailbox transfer operation is triggered when the internal timer
SLEEP bit set in the CAN_SR)
the MRDY signal in the CAN_MSR
each End Of Frame
reaches the mailbox trigger.
last_mailbox_number
AT91SAM7A3 Preliminary
register).
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