AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 106

• Manufacturer Part Number: AT91SAM7A3-AU
• Description: IC ARM7 MCU FLASH 256K 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A3-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, MMC, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: AT91SAM7xx
• No. Of I/o's: 62
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/SPI/I2S/TWI/USART/USB
• On-chip Adc: 2(8-chx10-bit)
• Number Of Timers: 3
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 60 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 60MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 20-6. Example of Partial Page Programming:
20.2.4.2
106
16 words
16 words
16 words
16 words
AT91SAM7A3 Preliminary
Lock and Unlock Operations
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
Erase All Flash
Page 7 erased
32 bits wide
Step 1.
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
...
...
...
...
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
Two errors can be detected in the MC_FSR register after a programming sequence:
The Flash technology requires that an erase must be done before programming. The entire
memory plane can be erased at the same time, or a page can be automatically erased by
clearing the NEBP bit in the MC_FMR register before writing the command in the MC_FCR
register.
By setting the NEBP bit in the MC_FMR register, a page can be programmed in several steps
if it has been erased before (see
Lock bits are associated with several pages in the embedded Flash memory plane. This
defines lock regions in the embedded Flash memory plane. They prevent writing/erasing pro-
tected pages.
Each lock region has its own lock bit that is readable in the highest bits of the Flash Status
Register (MC_FSR).
After production, the device may have some embedded Flash lock regions locked. These
locked regions are reserved for a default application. Refer to the product definition section for
the default embedded Flash mapping. Locked lock regions can be unlocked to be erased and
then programmed with another application or other data.
The lock and unlock commands are performed by defining the PAGEN field and by writing the
appropriate command (Set Lock Bit Command (SLB) or Clear Lock Bit Command (CLB))
in the Flash Command Register (MC_FCR). PAGEN defines one page number of the lock
region to be locked or unlocked. Writing in all the other bits of PAGEN has no effect.
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
• Programming Error: A bad keyword and/or an invalid command have been written in the
• Lock Error: The page to be programmed belongs to a locked region. A command must be
MC_FCR register.
previously run to unlock the corresponding region.
Programming of the second part of Page 7
FF
FF
FF
CA FE
CA FE
CA FE
FF
FF
FF
FF
FF
FF
(NEBP = 1)
32 bits wide
FF
FF
FF
FF
FF
FF
FF
FF
FF
Step 2.
...
...
...
...
Figure
FF
FF
FF
CA
CA
CA
FF
FF
FF
FF
FF
FF
FF
FF
FF
FE
FE
FE
FF
FF
FF
FF
FF
FF
20-6).
Programming of the third part of Page 7
CA FE
CA FE
CA FE
FF
FF
FF
DE CA
DE CA
DE CA
FF
FF
FF
(NEBP = 1)
32 bits wide
FF
FF
FF
FF
FF
FF
Step 3.
...
...
...
...
CA
CA
CA
FF
FF
FF
DE CA
DE CA
DE CA
FF
FF
FF
6042E–ATARM–14-Dec-06
FF
FF
FF
FF
FF
FF
FE
FE
FE