AT91SAM7A3-AU Atmel, AT91SAM7A3-AU Datasheet - Page 117
AT91SAM7A3-AU
Manufacturer Part Number
AT91SAM7A3-AU
Description
IC ARM7 MCU FLASH 256K 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7A3-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
60MHz
Connectivity
CAN, I²C, MMC, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Controller Family/series
AT91SAM7xx
No. Of I/o's
62
Ram Memory Size
32KB
Cpu Speed
60MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
60 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
62
Interface Type
CAN/SPI/I2S/TWI/USART/USB
On-chip Adc
2(8-chx10-bit)
Number Of Timers
3
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Ram Size
32 KB
Maximum Clock Frequency
60 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7A3-EK
Minimum Operating Temperature
- 40 C
Cpu Family
91S
Device Core Size
32b
Frequency (max)
60MHz
Total Internal Ram Size
32KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7A3-EK - KIT EVAL FOR AT91SAM7A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7A3-AU
Manufacturer:
MXIC
Quantity:
1 001
Company:
Part Number:
AT91SAM7A3-AU
Manufacturer:
Atmel
Quantity:
730
- Current page: 117 of 594
- Download datasheet (7Mb)
21.3.4
21.3.5
6042E–ATARM–14-Dec-06
Data Transfers
Priority of PDC Transfer Requests
If the counter is reprogrammed while the PDC is operating, the number of transfers is updated
and the PDC counts transfers from the new value.
Programming the Next Counter/Pointer registers chains the buffers. The counters are decre-
mented after each data transfer as stated above, but when the transfer counter reaches zero,
the values of the Next Counter/Pointer are loaded into the Counter/Pointer registers in order to
re-enable the triggers.
For each channel, two status bits indicate the end of the current buffer (ENDRX, ENDTX) and
the end of both current and next buffer (RXBUFF, TXBUFE). These bits are directly mapped to
the peripheral status register and can trigger an interrupt request to the AIC.
The peripheral end flag is automatically cleared when one of the counter-registers (Counter or
Next Counter Register) is written.
Note: When the Next Counter Register is loaded into the Counter Register, it is set to zero.
The peripheral triggers PDC transfers using transmit (TXRDY) and receive (RXRDY) signals.
When the peripheral receives an external character, it sends a Receive Ready signal to the
PDC which then requests access to the system bus. When access is granted, the PDC starts
a read of the peripheral Receive Holding Register (RHR) and then triggers a write in the
memory.
After each transfer, the relevant PDC memory pointer is incremented and the number of trans-
fers left is decremented. When the memory block size is reached, a signal is sent to the
peripheral and the transfer stops.
The same procedure is followed, in reverse, for transmit transfers.
The Peripheral DMA Controller handles transfer requests from the channel according to priori-
ties fixed for each product.These priorities are defined in the product datasheet.
If simultaneous requests of the same type (receiver or transmitter) occur on identical peripher-
als, the priority is determined by the numbering of the peripherals.
If transfer requests are not simultaneous, they are treated in the order they occurred.
Requests from the receivers are handled first and then followed by transmitter requests.
AT91SAM7A3 Preliminary
117
Related parts for AT91SAM7A3-AU
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
MCU ARM9 64K SRAM 144-LFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM9 MPU 217-LFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU ARM9 ULTRA LOW PWR 217-LFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU ARM9 324-TFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC MCU ARM9 SAMPLING 217CBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM9 MCU 217-LFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM9 MCU 208-PQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU ARM 512K HS FLASH 100-LQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU ARM 512K HS FLASH 100-TFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM9 MCU 200 MHZ 324-TFBGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM MCU 16BIT 128K 256BGA
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM7 MCU 32BIT 128K 64LQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM7 MCU FLASH 512K 128-LQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC ARM9 MPU 217-LFBGA
Manufacturer:
Atmel
Datasheet: