AT91SAM9XE128-QU Atmel, AT91SAM9XE128-QU Datasheet - Page 849

• Manufacturer Part Number: AT91SAM9XE128-QU
• Description: MCU ARM9 128K FLASH 208-PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE128-QU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6254C–ATARM–22-Jan-10
Doc. Rev
6254A
Comments
First issue. Unqualified version on ATP: 02-Mar-07/Qualified on 01-Feb-08
Product specific parts updated in this version before qualification.
Section 46.2 “AT91SAM9XE128/256/512 Errata - Revision A parts”
Section 46.2.6.3 “SDRAMC: JEDEC Standard
Section 46.2.2.1 “Matrix: FIXED_PRIORITY
Section 21.5.4 “Bus Matrix Master Remap Control
Section 22.7.3 “8-bit NAND
Section 22.7.3.1 “Software Configuration”
Section 11. “ARM926EJ-S
Section 46.2.14.5 “USART: TXD signal is floating in Modem and Hardware Handshaking modes”
Section 46.2.14.6 “USART: DCD is active High instead of Low.”
Section 5.1 “Power
Section 43.2 “DC
Temperature Junction info removed.
Section 7.2.1 “Matrix
Section 7.2.2 “Matrix
Section 7.2.3 “Masters to Slaves
EBI, EMAC and Peripheral Timings: TBD
Section 6.5 “PIO
Section 6.8 “Slow Clock Selection”
Table 7-3, “AT91SAM9XE128/256/512 Masters to Slaves Access,” on page
relations updated
Section 8.1.6.1 “GPNVMBit[3] = 0, Boot on Embedded
Section 8.2.4 “Error Corrected Code Controller”
Figure 9-3 on page
Figure 12-1 “Debug and Test Block
added
Section 2-1 “AT91SAM9XE128/256/512 Block
Section 6.8 “Slow Clock
Section 8.1.6 “Boot Strategies”
Section 9-1 “AT91SAM9XE128/256/512 System Controller Block
signals redefined from Embedded Flash.
Table 13-3, “Large Crystal Table (MHz) OSCSEL = 1,” on page
Section 13.3 “Device Initialization”
Section 40.5 “Typical
Section 40.2 “Block
Controllers”, first line updated w/Schmitt trigger detail.
Characteristics”updated VOL and VOH in
Supplies”, added caution on “constraints at startup”.
34, /3 divider removed.
Diagram”, removed warning on pull-down connection.
Masters”,
Slaves”,
Connection”, figure and text updated to correspond to on chip conditions.
Selection”, OSCEL tied to GNDBU or VDDBU
Processor”, removed Tightly-Coupled Memory Interface chapter.
Flash”, removed reference to NANDOE and NANDWE multiplexing from
typo on GPNVMBit[3] fixed.
Access”, master and slave identification lists updated.
in the sub list,
table moved to Electrical Characteristics,
Diagram”and
AT91SAM9XE128/256/512 Preliminary
Functionality”, added.
Compatability”, added.
Diagram”, ICache is 16 Kbytes
replaced to correspond to actual ECC installation.
Step c.
Figure 12-1 “Debug and Test Pin
Register”, removed RCB5, RCB4, RCB3, RCB2
ROM”, some lines deleted.
(OSCEL = 1 and bypass mode) added.
Table 43-2 on page
76, 1.367667 frequency added.
added to Errata.
Diagram”, “security bit” and “gpnvm”
added to Errata section
Table 43-14 on page 807
20, master/slave
800.
List”, NTRST pin
and
Change
Request Ref.
prod specs
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review
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