ADUC7129BSTZ126-RL Analog Devices Inc, ADUC7129BSTZ126-RL Datasheet - Page 51

• Manufacturer Part Number: ADUC7129BSTZ126-RL
• Description: IC DAS MCU ARM7 ADC/DDS 80-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7129BSTZ126-RL

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 38
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-LQFP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: ADUC7129BSTZ126-RLTR

DIGITAL PERIPHERALS
PWM GENERAL OVERVIEW
The ADuC7128/ADuC7129 integrate a six channel PWM inter-
face. The PWM outputs can be configured to drive an H-bridge
or can be used as standard PWM outputs. On power up, the PWM
outputs default to H-bridge mode. This ensures that the motor
is turned off by default. In standard PWM mode, the outputs
are arranged as three pairs of PWM pins. Users have control
over the period of each pair of outputs and over the duty cycle
of each individual output.
Table 63. PWM MMRs
Name
PWMCON1
PWM1COM1
PWM1COM2
PWM1COM3
PWM1LEN
PWM2COM1
PWM2COM2
PWM2COM3
PWM2LEN
PWM3COM1
PWM3COM2
PWM3COM3
PWM3LEN
PWMCON2
PWMICLR
In all modes, the PWMxCOMx MMRs controls the point at
which the PWM outputs change state. An example of the first pair
of PWM outputs (PWM1 and PWM2) is shown in Figure 49.
Table 64. PWMCON1 MMR Bit Designations
Bit
14
13
12
11
10
9
8
7
Name
SYNC
PWM6INV
PWM4NV
PWM2INV
PWMTRIP
ENA
PWMCP2
PWMCP1
Description
PWM Control
Compare Register 1 for PWM Outputs 1 and 2
Compare Register 2 for PWM Outputs 1 and 2
Compare Register 3 for PWM Outputs 1 and 2
Frequency Control for PWM Outputs 1 and 2
Compare Register 1 for PWM Outputs 3 and 4
Compare Register 2 for PWM Outputs 3 and 4
Compare Register 3 for PWM Outputs 3 and 4
Frequency Control for PWM Outputs 3 and 4
Compare Register 1 for PWM Outputs 5 and 6
Compare Register 2 for PWM Outputs 5 and 6
Compare Register 3 for PWM Outputs 5 and 6
Frequency Control for PWM Outputs 5 and 6
PWM Convert Start Control
PWM Interrupt Clear
Description
Enables PWM Synchronization.
Set to 1 by the user to invert PWM6.
Cleared by user to use PWM6 in normal mode.
Set to 1 by the user to invert PWM4.
Cleared by user to use PWM4 in normal mode.
Set to 1 by the user to invert PWM2.
Cleared by user to use PWM2 in normal mode.
Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an
interrupt is generated.
Cleared by user to disable the PWMTRIP interrupt.
If HOFF = 0 and HMODE = 1.
PWM Clock Prescaler Bits.
Sets UCLK divider.
Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low
transition on the SYNC pin.
Cleared by user to ignore transitions on the SYNC pin.
Set to 1 by the user to enable PWM outputs.
Cleared by user to disable PWM outputs.
If HOFF = 1 and HMODE = 1, see Table 65.
If not in H-Bridge mode, this bit has no effect.
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The PWM clock is selectable via PWMCON1 with one of the
following values: UCLK/2, 4, 8, 16, 32, 64, 128, or 256. The
length of a PWM period is defined by PWMxLEN.
The PWM waveforms are set by the count value of the 16-bit
timer and the compare registers contents as shown with the
PWM1 and PWM2 waveforms above.
The low-side waveform, PWM2, goes high when the timer
count reaches PWM1LEN, and it goes low when the timer
count reaches the value held in PWM1COM3 or when the
high-side waveform PWM1 goes low.
The high-side waveform, PWM1, goes high when the timer
count reaches the value held in PWM1COM1, and it goes low
when the timer count reaches the value held in PWM1COM2.
HIGH SIDE
LOW SIDE
(PWM1)
(PWM2)
PWM1COM3
PWM1COM2
PWM1COM1
PWM1LEN
Figure 49. PWM Timing
ADuC7128/ADuC7129