ADUC7129BSTZ126-RL Analog Devices Inc, ADUC7129BSTZ126-RL Datasheet - Page 62

• Manufacturer Part Number: ADUC7129BSTZ126-RL
• Description: IC DAS MCU ARM7 ADC/DDS 80-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7129BSTZ126-RL

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 38
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-LQFP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: ADUC7129BSTZ126-RLTR

ADuC702x Series
Table 87. COMxIEN1 MMR Bit Designations
Bit
7
6
5
4
3
2
1
0
Table 88. COMxIID1 MMR Bit Designations
Bit 3:1
Status Bits
000
110
101
011
010
001
000
Note that to receive a network address interrupt, the slave must
ensure that Bit 0 of COMxIEN0 (enable receive buffer full
interrupt) is set to 1.
1
0
0
0
0
0
0
Name
ENAM
E9BT
E9BR
ENI
E9BD
ETD
NABP
NAB
Bit 0
NINT
Priority
2
3
1
2
3
4
Description
Network Address Mode Enable Bit.
9-Bit Transmit Enable Bit.
9-Bit Receive Enable Bit.
Network Interrupt Enable Bit.
Word Length.
Transmitter Pin Driver Enable Bit.
Network Address Bit, Interrupt Polarity Bit.
Network Address Bit.
Definition
No Interrupt.
Matching Network Address.
Address Transmitted, Buffer Empty.
Receive Line Status Interrupt.
Receive Buffer Full Interrupt.
Transmit Buffer Empty Interrupt.
Modem Status Interrupt.
Set by user to enable network address mode.
Cleared by user to disable network address mode.
Set by user to enable 9-bit transmit. ENAM must be set.
Cleared by user to disable 9-bit transmit.
Set by user to enable 9-bit receive. ENAM must be set.
Cleared by user to disable 9-bit receive.
Set for 9-bit data. E9BT has to be cleared.
Cleared for 8-bit data.
Set by user to enable SOUT as an output in slave mode or multimaster mode.
Cleared by user; SOUT is three-state.
Set by user to transmit the slave’s address.
Cleared by user to transmit data.
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COMxADR is an 8-bit, read/write network address register that
holds the address checked for by the network addressable
UART. Upon receiving this address, the device interrupts the
processor and/or sets the appropriate status bit in COMxIID1.
Clearing Operation
Read COMxRX.
Write data to COMxTX or read COMxIID0.
Read COMxSTA0.
Read COMxRX.
Write data to COMxTX or read COMxIID0.
Read COMxSTA1 register.
Preliminary Technical Data