Z8F0431SJ020SG Zilog, Z8F0431SJ020SG Datasheet
Z8F0431SJ020SG
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Z8F0431SJ020SG Summary of contents
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... High-Performance 8-Bit Microcontrollers ® Z8 Encore! Product Specification PS025111-1207 ® Copyright ©2007 by Zilog , Inc. All rights reserved. www.zilog.com F0830 Series ...
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... TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS025111-1207 ...
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Revision History Each instance in Revision History of this document reflects a change to this document from its previous revision. For more details, refer to the corresponding pages and appro- priate links in the table below. Revision Date Level December ...
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Table of Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ADC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Trim Bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Oscillator Operation with an External RC Network . . . . . . . . . . . . . . . . . . . . . 151 Internal Precision Oscillator . . . . . . . . ...
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Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Power-On Reset (POR) • 2 3.6 V operating voltage • thirteen 5 V tolerant input pins • 20- and 28-pin packages PS025111-1207 ® MCU family of products are the first in a line of Zilog ® Z8 Encore! F0830 Series Product Specification ® ® CPU instructions. The Overview 1 ...
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Part Selection Guide Table 1 lists the basic features available for each device within the Z8 Encore! Series product line. See ...
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CPU Memory Bus Register Bus Timers Comparator GPIO Figure 1. Z8 Encore! PS025111-1207 System Oscillator Clock Control On-Chip Debugger Interrupt Controller NVDS ADC Controller ® F0830 Series Block Diagram ® Z8 Encore! F0830 Series Product Specification XTAL/RC Oscillator Internal ...
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... CPU and Peripheral Overview eZ8 CPU Features The eZ8 CPU, Zilog’s latest 8-bit CPU meets the continuing demand for faster and more code-efficient microcontrollers. The eZ8 CPU executes a superset of the original Z8 instruction set. The eZ8 CPU features include: • Direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory. • ...
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Non-Volatile Data Storage The Non-Volatile Data Storage (NVDS) uses a hybrid hardware/software scheme to implement a byte-programmable data memory and is capable of storing about 100,000 write cycles. Internal Precision Oscillator The Internal Precision Oscillator (IPO) with accuracy of +/- ...
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Reset Controller ® The Z8 Encore! RESET pin, Power-on reset, Watchdog Timer (WDT) time-out, STOP mode exit, or Voltage Brownout (VBO) warning signal. The RESET pin is bidirectional, that is, it functions as reset source as well as a reset ...
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Pin Description ® The Z8 Encore! pin configurations. This chapter describes the signals and the pin configurations for each of the package styles. For information regarding the physical package specifications, see Packaging on page 193. Available Packages Table 2 lists ...
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Z8F0231 • Z8F1233 The analog supply pins (AV replaced by PB6 and PB7. At reset, by default, all pins of Port A, B and C are in Input state. The alternate functionality is also disabled, so the pins function ...
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PC3/COUT/LED 16 PB0/ANA0 17 PB1/ANA1 18 PB2/ANA2 19 PB3/CLKIN/ANA3 20 Figure 4. Z8F0830 Series in 20-Pin QFN Package PS025111-1207 PA7/T1OUT 10 PA6/T1IN/T1OUT 9 PA5 8 20-Pin QFN PA4 7 PA3 ...
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PC3/COUT/LED PB0/ANA0 PB1/ANA1 PB2/ANA2 PB4/ANA7 PB5/VREF PB3/CLKIN/ANA3 Figure 5. Z8F0830 Series in 28-Pin QFN Package Signal Descriptions Table 3 describes the Z8 Encore! F0830 Series signals. See to determine the signals available for the specific package styles. PS025111-1207 18 21 ...
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Table 3. Signal Descriptions Signal Mnemonic I/O Description General-Purpose I/O Ports A–D PA[7:0] I/O Port A. These pins are used for general purpose I/O. PB[7:0] I/O Port B. These pins are used for general purpose I/O. PB6 and PB7 are ...
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Table 3. Signal Descriptions (Continued) Signal Mnemonic I/O Description Clock Input CLKIN I Clock input signal. This pin may be used to input a TTL-level signal to be used as the system clock. LED Drivers LED O Direct LED drive ...
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Table 4. Pin Characteristics (20- and 28-pin Devices) Active Low Symbol Reset or Mnemonic Direction Direction Active High AVDD N/A N/A AVSS N/A N/A DBG I/O I PA[7:0] I/O I PB[7:0] I/O I PC[7:0] I/O I RESET/ I/O I/O PD0 ...
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PS025111-1207 ® Z8 Encore! F0830 Series Product Specification Pin Description 14 ...
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... The following sections describe about these three address spaces. For more detailed information regarding the eZ8 CPU and its address space, refer to eZ8 CPU Core User Manual (UM0128) available for download at www.zilog.com. Register File The register file address space in the Z8 Encore! file consists of two sections: control registers and general purpose registers ...
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Flash memory addresses returns program memory addresses produces no effect. maps for the Z8 Encore! Table 5. Z8 Encore! F0830 Series Program Memory Maps Program Memory Address (Hex) Function Z8F0830 and Z8F0831 Products 0000–0001 0002–0003 0004–003D 003E–1FFF Z8F0430 ...
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... FE80–FFFF PS025111-1207 Z8 Encore! Product Specification ® F0830 Series Flash information area. The 128 byte to . When the information area access is FE00H FE7FH Zilog option bits Part Number 20-character ASCII alphanumeric code Left justified and filled with FH Reserved Reserved Reserved ® F0830 Series 17 ...
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PS025111-1207 ® Z8 Encore! F0830 Series Product Specification Address Space 18 ...
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Register Map Table 7 provides the address map for the register file of the Z8 Encore! devices. Not all devices and package styles in the Z8 Encore! F0830 Series support the ADC, or all of the GPIO Ports. Consider registers ...
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Table 7. Register File Address Map (Continued) Address (Hex) Register Description F73 ADC data low bits F74 ADC sample settling time F75 ADC sample time F76 Reserved F77–F7F Reserved Low Power Control F80 Power control 0 F81 Reserved LED Controller ...
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Table 7. Register File Address Map (Continued) Address (Hex) Register Description FD0 Port A address FD1 Port A control FD2 Port A input data FD3 Port A output data GPIO Port B FD4 Port B address FD5 Port B control ...
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Table 7. Register File Address Map (Continued) Address (Hex) Register Description FF9 Flash page select Flash sector protect FFA Flash programming frequency high byte FFB Flash programming frequency low byte eZ8 CPU FFC Flags FFD Register pointer FFE Stack pointer ...
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Reset and Stop Mode Recovery The reset controller in the Z8 Encore! Recovery operations typical operation, the following events can cause a reset: • Power-On Reset (POR) • Voltage Brownout (VBO) • Watchdog Timer time-out (when configured by ...
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Table 8. Reset and Stop Mode Recovery Characteristics and Latency (Continued) Reset Characteristics and Latency Reset Type Control Registers Stop Mode Recovery Unaffected, except WDT_CTL and OSC_CTL registers Stop Mode Recovery with Unaffected, except crystal oscillator enabled WDT_CTL and OSC_CTL ...
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Table 9. Reset Sources and Resulting Reset Type Operating Mode Reset Source NORMAL or HALT Power-On Reset/Voltage modes Brownout Watchdog Timer time-out when configured for reset RESET pin assertion On-Chip Debugger initiated reset (OCDCTL[0] set to 1) STOP mode Power-On ...
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V POR V VBO VDD = 0.0V Internal Precision Oscillator Crystal Oscillator Internal RESET signal Note: Not to Scale Voltage Brownout Reset The devices in the Z8 Encore! protection. The VBO circuit forces the device to the Reset state, when ...
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The Voltage Brownout circuit can be either enabled or disabled during STOP mode. Operations during STOP mode is set by the VBO_AO Flash option bit. See Bits on page 117 for information about configuring VBO_AO. VDD = 3 ...
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While the RESET input pin is asserted low, the Z8 Encore! in the Reset state. ...
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The following sections provide more detailed information about each of the Stop Mode Recovery sources. Table 10. Stop Mode Recovery Sources and Resulting Action Operating Mode Stop Mode Recovery Source STOP mode Watchdog Timer time-out ...
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Stop Mode Recovery Using the External RESET Pin When the Z8 Encore! is driven low, a system reset occurs. Because of a glitch filter operating on the RESET pin, the low pulse must be greater than the minimum width specified ...
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Reset or Stop Mode Recovery Event Power-on reset Reset using RESET pin assertion Reset using Watchdog Timer time-out Reset using the On-Chip Debugger (OCTCTL[1] set to 1) Reset from STOP mode using DBG pin driven Low Stop Mode Recovery using ...
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PS025111-1207 ® Z8 Encore! F0830 Series Product Specification Reset and Stop Mode Recovery 32 ...
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Low-Power Modes ® The Z8 Encore! of power reduction is provided by the STOP mode. The next level of power reduction is provided by the HALT mode. Further power savings can be implemented by disabling the individual peripheral blocks while ...
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HALT Mode Executing the eZ8 CPU HALT instruction places the device into HALT mode. In HALT mode, the operating characteristics are: • Primary oscillator is enabled and continues to operate. • System clock is enabled and continues to operate. • ...
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This register is only reset during a Power-On Reset sequence. Other system reset events do Note: not affect it. Table 12. Power Control Register 0 (PWRCTL0) BITS 7 6 Reserved FIELD 1 0 RESET R/W R/W R/W ADDR Reserved—Must be ...
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PS025111-1207 ® Z8 Encore! F0830 Series Product Specification Low-Power Modes 36 ...
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General Purpose Input/Output ® The Z8 Encore! for General Purpose Input/Output (GPIO) operations. Each port contains control and data registers. The GPIO control registers determine data direction, open-drain, output drive current, programmable pull-ups, Stop Mode Recovery functionality, and Alternate Pin ...
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System Port Output Data Register DATA D Q Bus System Clock Figure 8. GPIO Port Pin Block Diagram GPIO Alternate Functions Many of the GPIO port pins can be used for general purpose input/output and access to on- chip peripheral ...
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Direct LED Drive The port C pins provide a sinked current output, capable of driving an LED without requiring an external resistor. The output sinks current at programmable levels, 3 mA, 7 mA, 13 mA, and 20 mA. This mode ...
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Table 14. Port Alternate Function Mapping Port Pin Mnemonic PA0 T0IN/T0OUT Port A Reserved PA1 T0OUT Reserved PA2 Reserved Reserved PA3 Reserved Reserved PA4 Reserved Reserved PA5 Reserved Reserved PA6 T1IN/T1OUT Reserved PA7 ...
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Table 14. Port Alternate Function Mapping (Continued) Port Pin Mnemonic PB0 Reserved Port B ANA0 PB1 Reserved ANA1 PB2 Reserved ANA2 PB3 CLKIN ANA3 PB4 Reserved ANA7 PB5 Reserved VREF PB6 Reserved Reserved PB7 Reserved Reserved Note: Because there are ...
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Table 14. Port Alternate Function Mapping (Continued) Port Pin Mnemonic PC0 Reserved Port C ANA4/CINP/LED Drive PC1 Reserved ANA5/CINN/ LED Drive PC2 Reserved ANA6/LED PC3 COUT LED PC4 Reserved LED PC5 Reserved LED PC6 Reserved LED PC7 Reserved LED Port ...
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GPIO Control Register Definitions Four registers for each port provide access to GPIO control, input data, and output data. Table 15 lists these port registers. Use the Port A–D address and control registers together to provide access to subregisters for ...
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Port A–D Address Registers The Port A–D address registers select the GPIO port functionality accessible through the port A–D control registers. The port A–D address and control registers combine to provide access to all GPIO port controls (see Table 16. ...
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Table 17. Port A–D Control Registers (PxCTL) BITS 7 6 FIELD RESET R/W R/W R/W ADDR PCTL[7:0]—Port Control The port control register provides access to all subregisters that configure the GPIO port operation. Port A–D Data Direction Subregisters The Port ...
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Caution: Do not enable Alternate functions for GPIO port pins for which there is no associated Alternate function. Failure to follow this guideline can result in unpredictable operation. Table 19. Port A–D Alternate Function Subregisters (PxAF) BITS 7 6 AF7 ...
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Port A–D High Drive Enable Subregisters The Port A–D high drive enable subregister is accessed through the Port A–D control register by writing Setting the bits in the Port A–D high drive enable subregisters to 1 configures, the specified port ...
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Port A–D Pull-up Enable Subregisters The Port A–D pull-up enable subregister is accessed through the Port A–D control register by writing to the Port A–D address register. See 06H A–D pull-up enable subregisters, enables a weak internal resistive pull-up on ...
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Port A–D Alternate Function Set 2 Subregisters The Port A–D Alternate function set 2 subregister is accessed through the Port A–D control register by writing Alternate function set 2 subregisters select the Alternate function available at a port pin. Alternate ...
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Port A–D Output Data Register The Port A–D output data register controls the output data to the pins. See Table 27. Port A–D Output Data Register (PxOUT) BITS 7 6 POUT7 POUT6 FIELD 0 0 RESET R/W R/W R/W ADDR ...
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LED Drive Level High Register The LED drive level registers contain two control bits for each Port C pin. See These two bits selects one of four programmable current drive levels for each Port C pin. Each pin is individually ...
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PS025111-1207 ® Z8 Encore! F0830 Series Product Specification General Purpose Input/Output 52 ...
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... The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt controller has no effect on operation. For more information regarding interrupt servicing by the eZ8 CPU, refer to eZ8 CPU User Manual (UM0128) available for download at www.zilog.com. Interrupt Vector Listing Table 31 lists the interrupts available in order of priority ...
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Table 31. Trap and Interrupt Vectors in Order of Priority Program Memory Priority Vector Address Interrupt or Trap Source Highest 0002H Reset (not an interrupt) 0004H Watchdog Timer (see Watchdog Timer chapter) 003AH Primary oscillator fail trap (not an interrupt) ...
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Table 31. Trap and Interrupt Vectors in Order of Priority (Continued) Program Memory Priority Vector Address Interrupt or Trap Source Lowest 0036H Port C0, both input edges 0038H Reserved Architecture Figure 9 displays the interrupt controller block diagram. Port Interrupts ...
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Execution of an IRET (return from interrupt) instruction • Writing 1 to the IRQE bit in the interrupt control register Interrupts are globally disabled by any of the following actions: • Execution of a • eZ8 CPU acknowledgement of ...
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AND r0, MASK LDX IRQ0, r0 Caution: To avoid missing interrupts, use the following coding style to clear bits in the interrupt request 0 register: Good coding style that avoids lost interrupt requests: ANDX IRQ0, MASK Software Interrupt Assertion Program ...
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CPU can read the interrupt request 0 register to determine if any interrupt requests are pending. Table 32. Interrupt Request 0 Register (IRQ0) BITS 7 6 Reserved T1I FIELD 0 0 RESET ...
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No interrupt request is pending for GPIO Port interrupt request from GPIO Port A. PA6CI—Port A6 or comparator interrupt request interrupt request is pending for GPIO Port A or comparator. 1 ...
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Table 35. IRQ0 Enable and Priority Encoding IRQ0ENH[x] IRQ0ENL[x] Priority 0 0 Disabled 0 1 Level Level Level 3 where x indicates the register bits from 0–7. Table 36. IRQ0 Enable High Bit Register ...
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IRQ1 Enable High and Low Bit Registers Table 38 describes the priority control for IRQ1. The IRQ1 enable high and low bit registers (Table 39 interrupt request 1 register. Priority is generated by setting bits in each register. Table 38. ...
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IRQ2 Enable High and Low Bit Registers Table 41 describes the priority control for IRQ2. The IRQ2 enable high and low bit registers (Table 42 interrupt request 2 register. Priority is generated by setting bits in each register. Table 41. ...
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Reserved—Must be 0. C3ENL—Port C3 interrupt request enable low bit C2ENL—Port C2 interrupt request enable low bit C1ENL—Port C1 interrupt request enable low bit C0ENL—Port C0 interrupt request enable low bit Interrupt Edge Select Register The interrupt edge select (IRQES) ...
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PA6CS—PA6/Comparator selection 0 = PA6 is used for the interrupt caused by PA6CS interrupt request The comparator is used for the interrupt caused by PA6CS interrupt request. Reserved—Must be 0. Interrupt Control Register The interrupt control (IRQCTL) register ...
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Timers ® The Z8 Encore! can be used for timing, event counting, or generation of pulse width modulated (PWM) signals. The timers feature include: • 16-bit reload counter. • Programmable prescaler with prescale values ranging from 1 to 128. • ...
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Operation The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value into the timer reload high and low byte registers and setting the prescale value to 1. 0001H Maximum time-out delay is set by loading the ...
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In ONE-SHOT mode, the system clock always provides the timer input. The timer period is given by the following equation: One-Shot Mode Time-Out Period (s) CONTINUOUS Mode In CONTINUOUS mode, the timer counts up to the 16-bit reload value stored ...
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COUNTER Mode In COUNTER mode, the timer counts input transitions from a GPIO port pin. The timer input is taken from the GPIO port pin: timer input alternate function. The TPOL bit in the timer control register determines whether the ...
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COMPARATOR COUNTER Mode In COMPARATOR COUNTER mode, the timer counts the input transitions from the analog comparator output. The TPOL bit in the timer control register determines whether the count occurs on the rising edge or the falling edge of ...
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PWM SINGLE OUTPUT Mode In PWM SINGLE OUTPUT mode, the timer outputs a pulse width modulated (PWM) output signal through a GPIO port pin. The timer input is the system clock. The timer first counts up to 16-bit PWM match ...
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The PWM period is represented by the following equation: PWM Period ( initial starting value other than registers, use the ONE-SHOT mode equation to determine the first PWM time-out period. If TPOL bit is set to 0, the ...
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Follow the steps below for configuring a timer for PWM DUAL OUTPUT mode and for initiating the PWM operation: 1. Write to the timer control register to: Disable the timer – Configure the timer for PWM DUAL OUTPUT mode. Setting ...
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If TPOL is set to 1, the ratio of the PWM output high time to the total period is represented by: PWM Output High Time Ratio (%) CAPTURE Mode In CAPTURE mode, the current timer count value is recorded when ...
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Configure the associated GPIO port pin for the timer input alternate function. 7. Write to the timer control register to enable the timer and initiate counting. In CAPTURE mode, the elapsed time between the timer start and the Capture ...
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Reload events. You can configure the timer interrupt to be generated only at the input Capture event or the Reload event by setting TICONFIG field of the TxCTL1 register. 6. Configure the associated GPIO port pin for ...
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GATED Mode In GATED mode, the timer counts only when the timer input signal is in its Active state (asserted), as determined by the TPOL bit in the timer control register. When the timer input signal is asserted, counting begins. ...
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When the Capture event occurs, an interrupt is generated, the count value in the timer high and low byte registers is reset to INPCAP bit in TxCTL1 register is set to indicate that the timer interrupt is caused by ...
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A subsequent read from the timer low byte register returns the value in the holding register. This operation allows accurate reads of the ...
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Table 48. Timer 0–1 Low Byte Register (TxL) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR TH and TL—Timer high and low bytes These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value. Timer Reload ...
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Timer 0-1 PWM High and Low Byte Registers The timer 0-1 PWM high and low byte (TxPWMH and TxPWML) registers Table 52) controls ...
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Table 53. Timer 0–1 Control Register 0 (TxCTL0) BITS 7 6 TMODEHI TICONFIG FIELD 0 0 RESET R/W R/W R/W ADDR TMODEHI—Timer mode high bit This bit along with the TMODE field in TxCTL1 register determines the operating mode of ...
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Timer 0–1 Control Register 1 The timer 0–1 control (TxCTL1) registers enable/disable the timers, set the prescaler value, and determine the timer operating mode. Table 54. Timer 0–1 Control Register 1 (TxCTL1) BITS 7 6 TEN TPOL FIELD 0 0 ...
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COMPARE Mode When the timer is disabled, the timer output signal is set to the value of this bit. When the timer is enabled and reloaded, the timer output signal is complemented. GATED Mode 0 = Timer counts when the ...
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This reset ensures proper clock division each time the timer is restarted. • 000 = Divide by 1 • 001 = Divide by 2 • 010 = Divide by 4 • ...
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Watchdog Timer The Watchdog Timer (WDT) protects from corrupted or unreliable software, power faults, and other system-level problems, which may place the Z8 Encore! into unsuitable operating states. The features of Watchdog Timer include: • On-chip RC oscillator • A ...
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Table 55. Watchdog Timer Approximate Time-Out Delays (Continued) WDT Reload Value WDT Reload Value (Hex) (Decimal) 000400 FFFFFF 16,777,215 Watchdog Timer Refresh On first enable, the Watchdog Timer is loaded with the value in the Watchdog Timer reload registers. The ...
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WDT Interrupt in STOP Mode If configured to generate an interrupt when a time-out occurs and the Z8 Encore! Series devices are in STOP mode, the Watchdog Timer automatically initiates a Stop Mode Recovery and generates an interrupt request. Both ...
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The value in the Watchdog Timer reload registers is loaded into the counter when the Watchdog Timer is first enabled and every time ...
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Table 57. Watchdog Timer Reload Upper Byte Register (WDTU) BITS 7 6 FIELD 0 0 RESET R/W* R/W* R/W ADDR R/W* - Read returns the current WDT count value. Write sets the appropriate reload value. WDTU—WDT reload upper byte Most ...
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PS025111-1207 ® Z8 Encore! F0830 Series Product Specification Watchdog Timer 90 ...
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Analog-to-Digital Converter ® The Z8 Encore! Analog-to-Digital Converter (ADC). The ADC converts an analog input signal to a 10-bit binary number. The features of the SAR ADC include: • Eight analog input sources multiplexed with general purpose I/O ports • ...
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Internal Voltage Reference Generator Analog-to-Digital Converter Reference Input 10 Data Output Analog Input BUSY ADCLK ADCEN START Figure 11. Analog-to-Digital Converter Block Diagram Operation The ADC converts the analog input, ANA equation for calculating the digital value is represented by: ...
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ADC Timing Each ADC measurement consists of three phases: 1. Input sampling (programmable, minimum of 1.0 µs) 2. Sample-and-hold amplifier settling (programmable, minimum of 0.5 µs) 3. Conversion is 13 ADCLK cycles. Figure 12 displays the timing of an ADC ...
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ADC Interrupt The ADC can generate an interrupt request when a conversion has been completed. An interrupt request that is pending when the ADC is disabled is not cleared automatically. Reference Buffer The reference buffer, RBUF, supplies the reference voltage ...
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Bit Value Description Position (H) [7] ADC Start/Busy START 0 Writing to 0 has no effect. Reading a 0 indicates that the ADC is available to begin a conversion. 1 Writing to 1 starts a conversion. Reading a 1 indicates ...
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Table 61. ADC Data High Byte Register (ADCD_H) BITS 7 6 FIELD RESET R/W ADDR Bit Value Description Position (H) [7:0] 00h–FFh ADC high byte The last conversion output is held in the data registers until the next ADC conversion ...
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Sample Settling Time Register The sample settling time register, listed in SAMPLE/HOLD signal is asserted before the START signal is asserted, which begins the conversion. The number of clock cycles required for settling will vary from system to system depending ...
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Table 64. Sample Time (ADCST) BITS 7 6 Reserved FIELD 0 RESET R/W R/W ADDR Bit Value Description Position (H) [7:6] 0h Reserved—Must be 0. [5: Sample-hold time in number of system clock periods to meet 1 ...
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Comparator ® The Z8 Encore! pares two analog input signals. A GPIO ( input. The negative input ( internal reference. The output is available as an interrupt source or can be routed to an external pin using the GPIO multiplex. ...
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Table 65. Comparator Control Register (CMP0) BITS 7 6 Reserved INNSEL FIELD 0 0 RESET R/W R/W R/W ADDR Reserved GPIO pin always used as positive comparator input INNSEL—Signal select for negative input 0 = internal reference disabled, GPIO pin ...
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Flash Memory The products in the Z8 Encore! NVDS (2048 bytes with NVDS (4096 bytes with NVDS (8192 bytes with NVDS (12288 bytes with no NVDS) of non volatile Flash memory ...
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Sector 1 0200H 01FFH Sector 0 0000H 07FFH Sector 3 0600H 05FFH Sector 2 0400H 03FFH Sector 1 0200H 01FFH Sector 0 0000H PS025111-1207 Figure 14. 1K Flash with NVDS Figure 15. 2K Flash with NVDS ® Z8 Encore! ...
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Sector 7 0E00H 0DFFH Sector 6 0C00H 0BFFH Sector 5 0A00H 09FFH Sector 4 0800H 07FFH Sector 3 0600H 05FFH Sector 2 0400H 03FFH Sector 1 0200H 01FFH Sector 0 0000H PS025111-1207 Figure 16. 4K Flash with NVDS ® ...
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Sector 7 1C00H 18FFH Sector 6 1800H 17FFH Sector 5 1400H 13FFH Sector 4 1C00H 0FFFH Sector 3 0C00H 0BFFH Sector 2 0800H 07FFH Sector 1 0400H 03FFH Sector 0 0000H PS025111-1207 Figure 17. 8K Flash with NVDS ® ...
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... Sector 0 0000H Data Memory Address Space The Flash information area, including the Zilog Flash option bits, are located in the data memory address space. The Z8 Encore! prevent the user from writing to the eZ8 CPU data memory address space. Flash Information Area ...
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... The trim bits are handled differently than the other Zilog Flash option bits. The trim bits are the hybrid of the user option bits and the standard Zilog option bits. These trim bits must be user accessible for reading at all times using external registers, regardless of the state of bit 7 in the Flash page select register ...
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Reset Lock State 0 Write Page Select Register Write FCTL No 73H Yes Lock State 1 Write FCTL No 8CH Yes Write Page Select Register No Page Select values match? Yes Yes Page in Protected Sector? No Page Unlocked Program/Erase ...
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Flash Operation Timing Using the Flash Frequency Registers Before performing either a Program or Erase operation on Flash memory, the user must first configure the Flash frequency high and low byte registers. The Flash frequency registers allow programming and erasing ...
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Code Protection using Flash Controller Table 68. Flash Code Protection using the Flash Option Bits FHSWP FWP reset, the Flash controller is locked to prevent accidental program or erasure of the Flash ...
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... Byte programming can be accomplished using the On-Chip Debugger's write memory command or eZ8 CPU execution of the LDC or LDCI instructions. Refer to the eZ8 CPU User Manual (available for download at www.zilog.com) for the description of the and instructions. While the Flash controller programs the Flash memory, the eZ8 LDCI CPU idles, but the system clock and on-chip peripherals continue to operate ...
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... The device uses Flash memory, despite the maximum specified Flash size (except 12 KB mode with non-NVDS). User code accesses the lower flash, leaving the upper 4 K for Zilog memory. The NVDS is implemented by using Zilog memory for special purpose routines and for the data required by the routines. These ...
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... See The NVDS routines are triggered by a user code: CALL into Zilog memory. Code executing from Zilog memory must be able to read and write other locations within Zilog memory. User code must not be able to read or write Zilog memory. Flash Control Register Definitions ...
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Table 70. Flash Status Register (FSTAT) BITS 7 6 Reserved FIELD 0 0 RESET R R R/W ADDR Reserved—Must be 0. FSTAT—Flash controller status 000000 = Flash controller locked 000001 = First unlock command received (73H written) 000010 = Second ...
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Table 71. Flash Page Select Register (FPS) BITS 7 6 INFO_EN FIELD 0 0 RESET R/W R/W R/W ADDR INFO_EN—Information area enable 0 = Information area is not selected 1 = Information area is selected. The information area is mapped ...
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Flash Frequency High and Low Byte Registers The Flash frequency high and low byte registers combine to form a 16-bit value, FFREQ, to control timing for Flash Program and Erase operations. The 16-bit binary Flash frequency value must contain the ...
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PS025111-1207 ® Z8 Encore! F0830 Series Product Specification Flash Memory 116 ...
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Flash Option Bits Programmable Flash option bits allow user configuration of certain aspects of Z8 ® Encore! F0830 Series operation. The feature configuration data is stored in the Flash program memory and read during reset. The features available for control ...
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Option Bit Types User Option Bits The user option bits are contained in the first two bytes of program memory. User access to these bits is provided because these locations contain application specific device configurations. The information contained here is ...
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Table 75. Trim Bit Address Register (TRMADR) BITS 7 6 FIELD 0 0 RESET R/W R/W R/W ADDR Trim Bit Data Register This register contains the read or write data to access the trim option bits. Table 76. Trim Bit ...
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Flash Program Memory Address 0000H Table 78. Flash Option Bits at Program Memory Address 0000H BITS 7 6 WDT_RES WDT_AO FIELD U U RESET R/W R/W R/W ADDR Note Unchanged by Reset. R/W = Read/Write. WDT_RES—Watchdog Timer reset ...
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FWP—Flash write protect This option bit provides Flash program memory protection Programming and erasure disabled for all Flash program memory. Programming, page erase, and mass erase through user code is disabled. Mass erase is available using the On-Chip ...
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Trim Bit Address Space Table 80. Trim Bit Address Space Address Function 00h 01h 02h 03h 06h Trim Bit Address 0000H Table 81. Trim Option Bits at 0000H (ADCREF) BITS 7 6 ADCREF_TRIM FIELD RESET R/W ADDR Note ...
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The bit values used in Note: Trim Bit Address 0002H Table 83. Trim Option Bits at 0002H (TIPO) BITS 7 6 FIELD RESET R/W ADDR Note Unchanged by Reset. R/W = Read/Write. IPO_TRIM—Internal Precision Oscillator trim byte Contains ...
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VBO Trim Definition VBO_TRIM Trigger Voltage Level 000 001 101 110 100 111 The on-chip Flash only guarantee Write operation with voltage supply over 2.7 V, Write operation below 2.7 V will get unpredictable results. The bit values used in ...
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Table 86. ClkFlt Delay Control Definition DlyCtl3, DlyCtl2, DlyCtl1 000 001 010 011 100 101 110 111 Note: The variation is about 30% PS025111-1207 Z8 Encore! Low noise pulse on High noise pulse high signal (ns) on low signal (ns) ...
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PS025111-1207 ® Z8 Encore! F0830 Series Product Specification Flash Option Bits 126 ...
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... Flash 12 KB mode). This memory can perform over 100,000 write cycles. Operation The NVDS is implemented by special purpose Zilog memory not accessible. These special purpose routines use the Flash memory to store the data. The routines incorporate a dynamic addressing scheme to maximize the write/erase endurance of the Flash ...
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Byte Write To write a byte to the NVDS array, the user code must first push the address, then the data byte onto the stack. The user code issues a Write routine ( 0x20B3 working register R0. The bit fields ...
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R1. The bit fields of this status byte are defined in Table 88. Also, the user code should pop the address byte off the stack. The read routine uses 16 bytes of stack space ...
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A system reset (such as a pin reset or Watchdog Timer reset) that occurs during a write operation also perturbs the byte currently being written. All other bytes in the array are unperturbed. Optimizing NVDS Memory Usage for Execution Speed ...
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On-Chip Debugger ® The Z8 Encore! the following advanced debugging features: • Reading and writing of the register file • Reading and writing of program and data memory • Setting of breakpoints and watchpoints • Executing eZ8 CPU instructions Architecture ...
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Operation OCD Interface The On-Chip Debugger uses the DBG pin for communication with an external host. This one-pin interface is a bidirectional open-drain interface that transmits and receives data. Data transmission is half-duplex, which means transmission and data retrieval cannot ...
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RS-232 TX RS-232 RX Figure 22. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface (2) DEBUG Mode The operating characteristics of the devices in DEBUG mode are: • The eZ8 CPU fetch unit stops, idling the eZ8 CPU, ...
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Asserting the RESET pin low to initiate a reset • Driving the DBG pin low while the device is in STOP mode, initiates a system reset OCD Data Format The OCD interface uses the asynchronous data format defined for ...
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OCD Serial Errors The OCD can detect any of the following error conditions on the DBG pin: • Serial break (a minimum of nine continuous bits low) • Framing error (received • Transmit collision (simultaneous transmission by OCD and host ...
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On-Chip Debugger Commands The host communicates to the On-Chip Debugger by sending OCD commands using the DBG interface. During normal operation, only a subset of the OCD commands are available. In DEBUG mode, all OCD commands become available unless the ...
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Command Debug Command Byte Execute Instruction Reserved 13H–FFH In the following bulleted list of OCD commands, data and commands sent from the host to the OCD are identified by host is identified by • Read OCD Revision (00H)—The read OCD ...
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Write Program Counter (06H)—The write program counter command, writes the data that follows to the eZ8 CPU’s program counter (PC). If the device is not in DEBUG mode or if the Flash read protect option bit is enabled, the ...
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DBG 0AH ← DBG Program Memory Address[15:8] ← DBG Program Memory Address[7:0] ← DBG Size[15:8] ← DBG Size[7:0] ← DBG 1-65536 data bytes • Read Program Memory (0BH)—The read program memory command, reads data from program memory. This command ...
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FFFFH from issuing of the command until the OCD returns the data. The OCD reads the program memory, calculates the CRC value, and returns the result. The delay is a function of the program memory size and is approximately ...
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Table 91. OCD Control Register (OCDCTL) BITS 7 6 DBGMODE BRKEN FIELD 0 0 RESET R/W R/W R/W DBGMODE—DEBUG mode The device enters DEBUG mode when this bit is 1. When in DEBUG mode, the eZ8 CPU stops fetching ...
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OCD Status Register The OCD status register reports status information about the current state of the debugger and the system. Table 92. OCD Status Register (OCDSTAT) BITS 7 6 DBG HALT FIELD 0 0 RESET R R R/W DBG—Debug status ...
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Oscillator Control ® The Z8 Encore! these is user-selectable. • On-chip precision trimmed RC oscillator • On-chip oscillator using off-chip crystal or resonator • On-chip oscillator using external RC network • External clock drive • On-chip low precision Watchdog Timer ...
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Table 93. Oscillator Configuration and Selection (Continued) Clock Source Characteristics External RC • 32 kHz to 4 MHz oscillator • Accuracy dependent on external components External clock drive • MHz • Accuracy dependent on external clock source ...
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Clock Failure Detection and Recovery Primary Oscillator Failure The Z8F04xA family devices can generate non-maskable interrupt-like events when the primary oscillator fails. To maintain system function in this situation, the clock failure recovery circuitry automatically forces the Watchdog Timer Oscillator ...
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Oscillator Control Register Definitions Oscillator Control Register The oscillator control register (OSCCTL) enables/disables the various oscillator circuits, enables/disables the failure detection/recovery circuitry, and selects the primary oscillator, which becomes the system clock. The oscillator control register must be unlocked before ...
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Crystal oscillator or external RC oscillator functions as system clock 011 = Watchdog Timer Oscillator functions as system clock 100 = External clock signal on PB3 functions as system clock 101 = Reserved 110 = Reserved 111 = ...
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PS025111-1207 ® Z8 Encore! F0830 Series Product Specification Oscillator Control 148 ...
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Crystal Oscillator The products in the Z8 Encore! with external crystals with 32 kHz to 20 MHz frequencies. In addition, the oscillator supports external RC networks with oscillation frequencies MHz or ceramic resonators with frequencies up to ...
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MHz crystal specifications are provided in total power dissipation by the crystal. Printed circuit board layout must add no more than stray capacitance to either the X reduce the values of capacitors C XIN C1 = 22pF ...
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Oscillator Operation with an External RC Network Figure 26 displays a recommended configuration for connection with an external resistor- capacitor (RC) network. Figure 26.Connecting the On-Chip Oscillator to an External RC Network An external resistance value of 45 kΩ is ...
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4000 3750 3500 3250 3000 2750 2500 2250 2000 1750 1500 1250 1000 750 500 250 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 420 440 ...
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Internal Precision Oscillator The Internal Precision Oscillator (IPO) is designed for use without external components. You can either manually trim the oscillator for a non-standard frequency or use the automatic factory trimmed version to achieve a 5.53 MHz frequency with ...
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PS025111-1207 ® Z8 Encore! F0830 Series Product Specification Internal Precision Oscillator 154 ...
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CPU Instruction Set Assembly Language Programming Introduction The eZ8 CPU assembly language provides a means for writing an application program without concern for actual memory addresses or machine instruction formats. A program written in assembly language is called a ...
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Assembly Language Syntax For proper instruction execution, eZ8 CPU assembly language syntax requires that the operands be written as ‘destination, source’. After assembly, the object code usually has the operands in the order ‘source, destination’, but ordering is opcode dependent. ...
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Table 98. Notational Shorthand Notation Description b Bit cc Condition Code DA Direct Address ER Extended Addressing Register IM Immediate Data Ir Indirect Working Register IR Indirect Register Irr Indirect Working Register Pair IRR Indirect Register Pair p Polarity ...
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Table 99. Additional Symbols Symbol Definition dst Destination Operand src Source Operand @ Indirect Address Prefix SP Stack Pointer PC Program Counter FLAGS Flags Register RP Register Pointer # Immediate Operand Prefix B Binary Number Suffix % Hexadecimal Number Prefix ...
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Table 100 through number of operands required for each instruction. Some instructions appear in more than one table as these instructions can be considered as a subset of more than one category. Within these tables, the source operand is identified ...
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Table 101. Bit Manipulation Instructions Mnemonic Operands BCLR bit, dst BIT p, bit, dst BSET bit, dst BSWAP dst CCF — RCF — SCF — TCM dst, src TCMX dst, src TM dst, src TMX dst, src Table 102. Block ...
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Table 104. Load Instructions Mnemonic Operands Instruction CLR dst LD dst, src LDC dst, src LDCI dst, src LDE dst, src LDEI dst, src LDWX dst, src LDX dst, src LEA dst, X(src) Load Effective Address POP dst POPX dst ...
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Table 106. Program Control Instructions Mnemonic BRK BTJ BTJNZ BTJZ CALL DJNZ IRET RET TRAP Table 107. Rotate and Shift Instructions Mnemonic BSWAP RL RLC RR RRC SRA SRL SWAP PS025111-1207 Operands Instruction — ...
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CPU Instruction Summary Table 108 summarizes the eZ8 CPU instructions. The table identifies the addressing modes employed by the instruction, the effect upon the Flags register, the number of CPU clock cycles required for the instruction fetch, and the ...
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Table 108. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst AND src ANDX dst, src ATM Block all interrupt and DMA requests during execution of the next 3 instructions dst[bit] ← 0 BCLR bit, dst dst[bit] ...
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Table 108. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation CP dst, src dst - src CPC dst, src dst - src - C CPCX dst, src dst - src - C CPX dst, src dst - src dst ...
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Table 108. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst + 1 INC dst dst ← dst + 1 INCW dst FLAGS ← @SP IRET SP ← ← @SP SP ← SP ...
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Table 108. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← src LDC dst, src dst ← src LDCI dst, src r ← ← dst ← src LDE dst, src dst ...
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Table 108. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst OR src OR dst, src dst ← dst OR src ORX dst, src dst ← @SP POP dst SP ← dst ← @SP ...
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Table 108. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation RR dst dst RRC dst dst dst ← dst – src - C ...
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Table 108. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation dst ← dst – src SUB dst, src dst ← dst – src SUBX dst, src dst[7:4] ↔ dst[3:0] SWAP dst TCM dst, src (NOT dst) AND src TCMX ...
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Table 108. eZ8 CPU Instruction Summary (Continued) Assembly Mnemonic Symbolic Operation SP ← SP – 2 TRAP Vector @SP ← ← SP – 1 @SP ← FLAGS PC ← @Vector WDT dst ← dst XOR src XOR dst, ...
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Opcode Maps A description of the opcode map data and the abbreviations are provided in Figure 29 and Figure 30 instructions. Table 109 Opcode Upper Nibble First Operand After Assembly Figure 28. Opcode Map Cell Description PS025111-1207 on page 175 ...
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Table 109. Opcode Map Abbreviations Abbreviation Description b Bit position cc Condition code X 8-bit signed index or displacement DA Destination address ER Extended Addressing register IM Immediate data value Ir Indirect Working Register IR Indirect register Irr Indirect Working ...
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BRK SRP ADD ADD 0 IM r1,r2 r1,Ir2 2.2 2.3 2.3 2.4 RLC RLC ADC ADC 1 R1 IR1 r1,r2 r1,Ir2 2.2 2.3 2.3 2.4 INC INC SUB SUB 2 R1 IR1 ...
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PUSH 3.3 3.4 4.3 CPC CPC CPC A r1,r2 r1,Ir2 R2,R1 B 3.2 3.3 SRL SRL C R1 IR1 Figure ...
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PS025111-1207 ® Z8 Encore! F0830 Series Product Specification Opcode Maps 176 ...
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Electrical Characteristics The data in this chapter is pre-qualification and pre-characterization and is subject to change. Additional electrical characteristics may be found in the individual chapters. Absolute Maximum Ratings Stresses greater than those listed in These ratings are stress ratings ...
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DC Characteristics Table 111 lists the DC characteristics of the Z8 Encore! voltages are referenced to V Table 111. DC Characteristics °C to +70 ° Symbol Parameter Min V Supply Voltage DD V Low Level ...
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Table 111. DC Characteristics (Continued °C to +70 ° Symbol Parameter Min I Controlled LED Current Drive C GPIO Port Pad PAD Capacitance C XIN Pad XIN Capacitance C XOUT Pad XOUT Capacitance I Weak ...
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V, versus Figure 31 the system clock frequency in HALT mode. Figure 31. ICC Versus System Clock Frequency (HALT mode) PS025111-1207 ® Z8 Encore! F0830 Series Product Specification Electrical ...
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Figure 32 NORMAL mode. Figure 32. ICC Versus System Clock Frequency (NORMAL mode) AC Characteristics The section provides information about the AC characteristics and timing. All AC timing information ...
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Table 112. AC Characteristics (Continued) Symbol Parameter F Internal Precision IPO Oscillator Frequency F Internal Precision IPO Oscillator Frequency F Internal Precision IPO Oscillator Frequency F Internal Precision IPO Oscillator Frequency F Internal Precision IPO Oscillator Frequency T System Clock ...
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On-Chip Peripheral AC and DC Electrical Characteristics Table 113. Power-On Reset and Voltage Brownout Electrical Characteristics and Timing T = 0°C to +70°C A Symbol Parameter Min V Power-On Reset POR Voltage Threshold V Voltage Brownout VBO Reset Voltage Threshold ...
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Table 113. Power-On Reset and Voltage Brownout Electrical Characteristics and Timing (Continued 0°C to +70°C A Symbol Parameter Min T Stop Mode SMR Recovery with crystal oscillator enabled T Voltage Brownout VBO Pulse Rejection Period T Time for ...
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Table 114. Flash Memory Electrical Characteristics and Timing V = 2 °C to +70 °C A Parameter Min Typ Flash Byte Read Time Flash Byte Program Time Flash Page Erase Time Flash Mass ...
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Table 115. Watchdog Timer Electrical Characteristics and Timing Symbol Parameter Active power consumption F WDT oscillator WDT frequency Table 116. Non-Volatile Data Storage V = 2 °C to +70 °C A Parameter Min ...
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Table 117. Analog-to-Digital Converter Electrical Characteristics and Timing Symbol Parameter Min Resolution Differential 1 Nonlinearity (DNL) Integral Nonlinearity 1 (INL) Gain Error Offset Error Vref On chip reference Active Power Consumption Power Down Current Zin Input ...
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Table 118. Comparator Electrical Characteristics Symbol Parameter V Input DC Offset OS V Programmable CREF Internal Reference Voltage Range V Programmable CREF internal reference voltage T Propagation delay PROP V Input hysteresis HYS General Purpose I/O Port Input Data Sample ...
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Table 119. GPIO Port Input Timing Parameter Abbreviation T Port Input Transition to XIN Rise Setup Time S_PORT (Not pictured) T XIN Rise to Port Input Transition Hold Time H_PORT (Not pictured) T GPIO Port Pin Pulse Width to ensure ...
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On-Chip Debugger Timing and Table 121 Figure 35 specifications assume maximum rise and fall time. XIN T1 DBG (Output) DBG (Input) Table 121. On-Chip Debugger Timing Parameter Abbreviation DBG T XIN Rise to DBG Valid Delay 1 ...