Z8F0431SJ020SG Zilog, Z8F0431SJ020SG Datasheet - Page 67

• Manufacturer Part Number: Z8F0431SJ020SG
• Description: IC ENCORE XP MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F0431SJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4627-5

Interrupt Control Register Definitions
PS025111-1207
Caution:
Caution:
Caution:
Software Interrupt Assertion
Interrupt Request 0 Register
Program code can generate interrupts directly. Writing 1 to the correct bit in the interrupt
request register triggers an interrupt (assuming that interrupt is enabled). When the
interrupt request is acknowledged by the eZ8 CPU, the bit in the interrupt request register
is automatically cleared to 0.
The interrupt control registers enable individual interrupts, set interrupt priorities, and
indicate interrupt requests for all the interrupts other than the Watchdog Timer interrupt,
the primary oscillator fail trap, and the Watchdog Oscillator fail trap interrupts.
The interrupt request 0 (IRQ0) register stores the interrupt requests for both vectored and
polled interrupts. See
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
To avoid missing interrupts, use the following coding style to clear bits in the interrupt
request 0 register:
The coding style listed below that generates software interrupts by setting bits in the
interrupt request registers is not recommended. All incoming interrupts received
between execution of the first LDX command and the final LDX command are lost.
To avoid missing interrupts, use the following coding style to set bits in the interrupt
request registers:
Good coding style that avoids lost interrupt requests:
Poor coding style that can result in lost interrupt requests:
Good coding style that avoids lost interrupt requests:
AND r0, MASK
LDX IRQ0, r0
ANDX IRQ0, MASK
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
ORX IRQ0, MASK
Table
32. When a request is sent to the interrupt controller, the
Z8 Encore!
Product Specification
®
Interrupt Controller
F0830 Series
57