Z8F0431SJ020SG Zilog, Z8F0431SJ020SG Datasheet - Page 84

• Manufacturer Part Number: Z8F0431SJ020SG
• Description: IC ENCORE XP MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F0431SJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4627-5

PS025111-1207
6. Configure the associated GPIO port pin for the timer input alternate function.
7. Write to the timer control register to enable the timer and initiate counting.
In CAPTURE mode, the elapsed time between the timer start and the Capture event can be
calculated using the following equation:
Capture Elapsed Time (s)
CAPTURE RESTART Mode
In CAPTURE RESTART mode, the current timer count value is recorded when the
acceptable external timer input transition occurs. The capture count value is written to the
timer PWM high and low byte registers. The timer input is the system clock. The TPOL
bit in the timer control register determines whether the capture occurs on a rising edge or a
falling edge of the timer input signal. When the capture event occurs, an interrupt is
generated and the count value in the timer high and low byte registers is reset to
and counting resumes. The INPCAP bit in TxCTL1 register is set to indicate, the timer
interrupt is caused by an input Capture event.
If no Capture event occurs, the timer counts up to 16-bit compare value stored in the timer
reload high and low byte registers. On reaching the reload value, the timer generates an
interrupt, the count value in the timer high and low byte registers is reset to
counting resumes. The INPCAP bit in TxCTL1 register is cleared to indicate the timer
interrupt is not caused by an input Capture event.
Follow the steps below for configuring a timer for CAPTURE RESTART mode and for
initiating the count:
1. Write to the timer control register to:
2. Write to the timer high and low byte registers to set the starting count value (typically
3. Write to the timer reload high and low byte registers to set the reload value.
4. Clear the timer PWM high and low byte registers to 0000H. This allows user software
5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
–
–
–
–
0001H
to determine if interrupts are generated by either a Capture event or a reload. If the
PWM high and low byte registers still contain 0000H after the interrupt, the interrupt
were generated by a reload.
to the relevant interrupt registers. By default, the timer interrupt is generated for both
Disable the timer
Configure the timer for CAPTURE RESTART mode. Setting the mode also
involves writing to TMODEHI bit in TxCTL1 register.
Set the prescale value.
Set the capture edge (rising or falling) for the timer input.
).
=
(
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Capture Value Start Value
System Clock Frequency (Hz)
–
Z8 Encore!
)
Product Specification
×
Prescale
®
F0830 Series
0001H
0001H
and
Timers
74