Z8F0431SJ020SG Zilog, Z8F0431SJ020SG Datasheet - Page 140

• Manufacturer Part Number: Z8F0431SJ020SG
• Description: IC ENCORE XP MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F0431SJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4627-5

PS025111-1207
Note:
Optimizing NVDS Memory Usage for Execution Speed
A system reset (such as a pin reset or Watchdog Timer reset) that occurs during a write
operation also perturbs the byte currently being written. All other bytes in the array are
unperturbed.
As listed in
trade-off for minimizing the frequency of writes that require post-write page erases. The
NVDS read time of address N is a function of the number of writes to addresses other than
N since the most recent write to address N, as well as the number of writes since the most
recent page erase. Neglecting effects caused by page erases and results caused by the
initial condition in which the NVDS is blank, a rule of thumb is that every write since the
most recent page erase causes read times of unwritten addresses to increase by 0.8 µs, up
to a maximum of 258 µs.
Table 89.NVDS Read Time
For every 200 writes, a maintenance operation is necessary. In this rare occurrence, the
write takes up to 58 ms to complete.
If NVDS read performance is critical to your software architecture, you can optimize your
code for speed by using any of the methods listed below.
1. Periodically refresh all addresses that are used. This is the most useful method. The
2. Use as few unique addresses as possible. This helps to optimize the impact of
Operation
Read
Write
Illegal Read
Illegal Write
optimal use of NVDS in terms of speed is to rotate the writes evenly among all
addresses planned to use, bringing all reads closer to the minimum read time. Because
the minimum read time is much less than the write time, however, actual speed
benefits are not always realized.
refreshing.
Table
89, the NVDS read time varies drastically, this discrepancy being a
Minimum
Latency (
71
126
6
7
µs
)
Maximum
Latency (
258
136
6
7
µs
)
Z8 Encore!
Product Specification
Non-Volatile Data Storage
®
F0830 Series
130