Z8F0431SJ020SG Zilog, Z8F0431SJ020SG Datasheet - Page 93

• Manufacturer Part Number: Z8F0431SJ020SG
• Description: IC ENCORE XP MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F0431SJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4627-5

PS025111-1207
Caution:
Caution:
PRES—Prescale value.
The timer input clock is divided by 2
When the timer output alternate function TxOUT on a GPIO port pin is enabled, TxOUT
will change to whatever state the TPOL bit is in. The timer does not need to be enabled
for that to happen. Also, the port data direction sub register is not needed to be set to
output on TxOUT. Changing the TPOL bit when the timer is enabled and running does
not immediately change the polarity TxOUT.
COMPARE Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When
the timer is enabled and reloaded, the timer output signal is complemented.
GATED Mode
0 = Timer counts when the timer input signal is high (1) and interrupts are generated
on the falling edge of the timer input.
1 = Timer counts when the timer input signal is low (0) and interrupts are generated on
the rising edge of the timer input.
CAPTURE/COMPARE Mode
0 = Counting is started on the first rising edge of the timer input signal. The current
count is captured on subsequent rising edges of the timer input signal.
1 = Counting is started on the first falling edge of the timer input signal. The current
count is captured on subsequent falling edges of the timer input signal.
PWM DUAL OUTPUT Mode
0 = Timer output is forced low (0) and timer output complement is forced high (1),
when the timer is disabled. When enabled and the PWM count matches, the timer
output is forced high (1) and forced low (0) when enabled and reloaded. When
enabled and the PWM count matches, the timer output complement is forced low (0)
and forced high (1) when enabled and reloaded.
1 = Timer output is forced high (1) and timer output complement is forced low (0)
when the timer is disabled. When enabled and the PWM count matches, the timer
output is forced low (0) and forced high (1) when enabled and reloaded.When enabled
and the PWM count matches, the timer output complement is forced high (1) and
forced low (0) when enabled and reloaded. The PWMD field in the TxCTL0 register
determines an optional added delay on the assertion (low to high) transition of both
timer output and timer output complement for deadband generation.
CAPTURE RESTART Mode
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
COMPARATOR COUNTER Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When
the timer is enabled, the timer output signal is complemented on timer reload.
PRES
, where PRES can be set from 0 to 7. The
Z8 Encore!
Product Specification
®
F0830 Series
Timers
83