Z8F0431SJ020SG Zilog, Z8F0431SJ020SG Datasheet - Page 144

• Manufacturer Part Number: Z8F0431SJ020SG
• Description: IC ENCORE XP MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F0431SJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4627-5

PS025111-1207
START
OCD Data Format
OCD Auto-Baud Detector/Generator
Table 90. OCD Baud-Rate Limits
•
•
The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 start bit, 8 data bits (least-significant bit first), and 1 stop bit. See
Figure
To run over a range of baud rates (data bits per second) with various system clock
frequencies, the On-Chip Debugger contains an auto-baud detector/generator. After a
reset, the OCD is idle until it receives data. The OCD requires that the first character sent
from the host is the character
Start bit plus 7 data bits), framed between high bits. The auto-baud detector measures this
period and sets the OCD baud rate generator accordingly.
The auto-baud detector/generator is clocked by the system clock. The minimum baud rate
is the system clock frequency divided by 512. For optimal operation with asynchronous
datastreams, the maximum recommended baud rate is the system clock frequency divided
by 8. The maximum possible baud rate for asynchronous datastreams is the system clock
frequency divided by 4, but this theoretical maximum is possible only for low noise
designs with clean signals.
rates for sample crystal frequencies.
If the OCD receives a serial break (nine or more continuous bits low), the auto-baud
detector/generator resets. Reconfigure the auto-baud detector/generator by sending
System Clock
Frequency
(MHz)
D0
0.032768 (32 KHz)
Asserting the RESET pin low to initiate a reset
Driving the DBG pin low while the device is in STOP mode, initiates a system reset
23.
20.0
D1
1.0
D2
Figure 23.OCD Data Format
Recommended
Maximum Baud
Rate (kbps)
Table 90
80H
D3
2500.0
125.0
4.096
. The character
lists minimum and recommended maximum baud
D4
Recommended
Standard PC
Baud Rate (bps)
80H
1,843,200
115,200
D5
2400
has eight continuous bits low (one
Z8 Encore!
D6
Product Specification
Minimum Baud
Rate (kbps)
0.064
D7
1.95
®
39
On-Chip Debugger
F0830 Series
STOP
80H
.
134