Z8F0431SJ020SG Zilog, Z8F0431SJ020SG Datasheet - Page 151

• Manufacturer Part Number: Z8F0431SJ020SG
• Description: IC ENCORE XP MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F0431SJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4627-5

Table 91. OCD Control Register (OCDCTL)
.
BITS
FIELD
RESET
R/W
PS025111-1207
DBGMODE
R/W
0
7
DBGMODE—DEBUG mode
The device enters DEBUG mode when this bit is 1. When in DEBUG mode, the eZ8 CPU
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is
automatically set when a
Flash read protect option bit is enabled, this bit can only be cleared by resetting the device.
It cannot be written to 0.
0 = The Z8 Encore! F0830 Series device is operating in NORMAL mode
1 = The Z8 Encore! F0830 Series device is in DEBUG mode
BRKEN—Breakpoint enable
This bit controls the behavior of the
are disabled and the
when a
automatically set to 1.
0 = Breakpoints are disabled
1 = Breakpoints are enabled
DBGACK—Debug acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a
Debug acknowledge character (
0 = Debug acknowledge is disabled
1 = Debug acknowledge is enabled
Reserved—Must be 0
RST—Reset
Setting this bit to 1 resets the Z8F04xA family device. The device goes through a normal
Power-on reset sequence with the exception that the On-Chip Debugger is not reset. This
bit is automatically cleared to 0 at the end of reset.
0 = No effect
1 = Reset the Flash read protect option bit device
BRK
BRKEN
R/W
6
0
instruction is decoded, the
DBGACK
BRK
R/W
5
0
instruction behaves similar to an NOP instruction. If this bit is 1
BRK
instruction is decoded and breakpoints are enabled. If the
FFH
R
0
4
BRK
) to the host when a breakpoint occurs.
DBGMODE
instruction (opcode
R
3
0
bit of the OCDCTL register is
Reserved
R
Z8 Encore!
0
2
00H
Product Specification
). By default, breakpoints
R
1
0
®
On-Chip Debugger
F0830 Series
RST
R/W
0
0
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