Z8F0431SJ020SG Zilog, Z8F0431SJ020SG Datasheet - Page 68

• Manufacturer Part Number: Z8F0431SJ020SG
• Description: IC ENCORE XP MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F0431SJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4627-5

Table 32. Interrupt Request 0 Register (IRQ0)
Table 33. Interrupt Request 1 Register (IRQ1)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS025111-1207
Interrupt Request 1 Register
Reserved
PA7I
R/W
R/W
0
0
7
7
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the interrupt
request 0 register to determine if any interrupt requests are pending.
Reserved—Must be 0.
T1I—Timer 1 interrupt request
0 = No interrupt request is pending for timer 1.
1 = An interrupt request from timer 1 is awaiting service.
T0I—Timer 0 interrupt request
0 = No interrupt request is pending for timer 0.
1 = An interrupt request from timer 0 is awaiting service.
ADCI—ADC interrupt request
0 = No interrupt request is pending for the analog-to-digital converter.
1 = An interrupt request from the analog-to-digital converter is awaiting service.
The interrupt request 1 (IRQ1) register stores interrupt requests for both vectored and
polled interrupts. See
corresponding bit in the IRQ1 register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the interrupt
request 1 register to determine if any interrupt requests are pending.
PA7I—Port A7
PA6CI
R/W
R/W
T1I
6
0
6
0
PA5I
R/W
Table
R/W
T0I
5
0
5
0
33. When a request is sent to the interrupt controller, the
Reserved Reserved Reserved Reserved
PA4I
R/W
R/W
0
0
4
4
FC0H
FC3H
PA3I
R/W
R/W
3
0
3
0
PA2I
R/W
R/W
Z8 Encore!
0
0
2
2
Product Specification
PA1I
R/W
R/W
1
0
1
0
®
Interrupt Controller
F0830 Series
ADCI
PA0I
R/W
R/W
0
0
0
0
58