Z8F0431SJ020SG Zilog, Z8F0431SJ020SG Datasheet - Page 81

• Manufacturer Part Number: Z8F0431SJ020SG
• Description: IC ENCORE XP MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F0431SJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4627-5

PS025111-1207
The PWM period is represented by the following equation:
If an initial starting value other than
registers, use the ONE-SHOT mode equation to determine the first PWM time-out period.
If TPOL bit is set to 0, the ratio of the PWM output high time to the total period is
represented by:
PWM Output High Time Ratio (%)
If TPOL bit is set to 1, the ratio of the PWM output high time to the total period is
represented by:
PWM DUAL OUTPUT Mode
In PWM DUAL OUTPUT mode, the timer outputs a PWM output signal pair (basic PWM
signal and its complement) through two GPIO port pins. The timer input is the system
clock. The timer first counts up to 16-bit PWM match value stored in the timer PWM high
and low byte registers. When the timer count value matches the PWM value, the timer
output toggles. The timer continues counting until it reaches the reload value stored in the
timer reload high and low byte registers. On reaching the reload value, the timer generates
an interrupt, the count value in the timer high and low byte registers is reset to
counting resumes.
If the TPOL bit in the timer control register is set to 1, the timer output signal begins as a
high (1) and transitions to a low (0) when the timer value matches the PWM value. The
timer output signal returns to a high (1) after the timer reaches the reload value and is reset
to
If the TPOL bit in the timer control register is set to 0, the timer output signal begins as a
low (0) and transitions to a high (1) when the timer value matches the PWM value. The
timer output signal returns to a low (0) after the timer reaches the reload value and is reset
to
The timer also generates a second PWM output signal: the timer output complement. The
timer output complement is the complement of the timer output PWM signal. A
programmable deadband delay can be configured to time delay (0 to 128 system clock
cycles) PWM output transitions on these two pins from a low to a high (inactive to active).
This ensures a time gap between the deassertion of one PWM output to the assertion of its
complement.
PWM Output High Time Ratio (%)
PWM Period (s)
0001H
0001H
.
.
=
--------------------------------------------------------------------------- -
System Clock Frequency (Hz)
Reload Value
0001H
=
=
×
Reload Value PWM Value
----------------------------------------------------------------------- -
Prescale
--------------------------------- -
Reload Value
PWM Value
is loaded into the timer high and low byte
Reload Value
–
×
100
Z8 Encore!
Product Specification
®
×
100
F0830 Series
0001H
Timers
and
71