C8051F365-GM Silicon Laboratories Inc, C8051F365-GM Datasheet - Page 114
![IC 8051 MCU 32K FLASH 28-QFN](/photos/12/27/122713/c8051f365-gm_sml.jpg)
C8051F365-GM
Manufacturer Part Number
C8051F365-GM
Description
IC 8051 MCU 32K FLASH 28-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Specifications of C8051F365-GM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
28-QFN
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
Package
28QFN
Device Core
8051
Family Name
C8051F36x
Maximum Speed
100 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1647
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F365-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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- Download datasheet (3Mb)
C8051F360/1/2/3/4/5/6/7/8/9
114
Bits 7–2: UNUSED. Read = 000000b. Write = don’t care.
Bit 1:
Bit 0:
Bits 7–2: UNUSED. Read = 000000b. Write = don’t care.
Bit 1:
Bit 0:
SFR Page:
SFR Address:
SFR Page:
SFR Address:
R/W
R/W
Bit7
Bit7
–
–
EMAT: Enable Port Match Interrupt.
This bit sets the masking of the Port Match interrupt.
0: Disable the Port Match interrupt.
1: Enable the Port Match interrupt.
UNUSED. Read = 0b. Write = don’t care.
PMAT: Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
UNUSED. Read = 0b. Write = don’t care.
all pages
0xE7
F
0xCF
R/W
R/W
Bit6
Bit6
SFR Definition 10.6. EIP2: Extended Interrupt Priority 2
SFR Definition 10.5. EIE2: Extended Interrupt Enable 2
–
–
R/W
R/W
Bit5
Bit5
–
–
R/W
R/W
Bit4
Bit4
–
–
Rev. 1.0
R/W
R/W
Bit3
Bit3
–
–
R/W
R/W
Bit2
Bit2
–
–
EMAT
PMAT
R/W
R/W
Bit1
Bit1
R/W
R/W
Bit0
Bit0
–
–
00000000
00000000
Reset Value
Reset Value
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