C8051F365-GM Silicon Laboratories Inc, C8051F365-GM Datasheet - Page 180
![IC 8051 MCU 32K FLASH 28-QFN](/photos/12/27/122713/c8051f365-gm_sml.jpg)
C8051F365-GM
Manufacturer Part Number
C8051F365-GM
Description
IC 8051 MCU 32K FLASH 28-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Specifications of C8051F365-GM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
28-QFN
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
Package
28QFN
Device Core
8051
Family Name
C8051F36x
Maximum Speed
100 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1647
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F365-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
- Current page: 180 of 288
- Download datasheet (3Mb)
C8051F360/1/2/3/4/5/6/7/8/9
To shut down the PLL, the system clock should be switched to the internal oscillator or a stable external
clock source, using the CLKSEL register. Next, disable the PLL by setting PLLEN (PLL0CN.1) to ‘0’.
Finally, the PLL can be powered off, by setting PLLPWR (PLL0CN.0) to ‘0’. Note that the PLLEN and PLL-
PWR bits can be cleared at the same time.
180
Bits 7–5: UNUSED. Read = 000b. Write = don’t care.
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Bits 7–5: UNUSED. Read = 000b. Write = don’t care.
Bits 4–0: PLLM4–0: PLL Reference Clock Pre-divider.
SFR Page:
SFR Address:
SFR Page:
SFR Address:
R/W
R/W
Bit7
Bit7
–
–
PLLLCK: PLL Lock Flag.
0: PLL Frequency is not locked.
1: PLL Frequency is locked.
RESERVED. Read = 0b. Must Write 0b.
PLLSRC: PLL Reference Clock Source Select Bit.
0: PLL Reference Clock Source is Internal Oscillator.
1: PLL Reference Clock Source is External Oscillator.
PLLEN: PLL Enable Bit.
0: PLL is held in reset.
1: PLL is enabled. PLLPWR must be ‘1’.
PLLPWR: PLL Power Enable.
0: PLL bias generator is de-activated. No static power is consumed.
1: PLL bias generator is active. Must be set for PLL to operate.
These bits select the pre-divide value of the PLL reference clock. When set to any non-zero
value, the reference clock will be divided by the value in PLLM4–0. When set to ‘00000b’,
the reference clock will be divided by 32.
F
0xB3
F
0xA9
R/W
R/W
Bit6
Bit6
–
–
SFR Definition 16.7. PLL0DIV: PLL Pre-divider
SFR Definition 16.6. PLL0CN: PLL Control
R/W
R/W
Bit5
Bit5
–
–
PLLLCK
PLLM4
R/W
Bit4
Bit4
R
Reserved
Rev. 1.0
PLLM3
R/W
Bit3
R/W
Bit3
PLLM2
PLLSRC
R/W
Bit2
R/W
Bit2
PLLM1
PLLEN
R/W
Bit1
R/W
Bit1
PLLM0
PLLPWR 00000000
R/W
Bit0
R/W
Bit0
00000001
Reset Value
Reset Value
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