C8051F365-GM Silicon Laboratories Inc, C8051F365-GM Datasheet - Page 267
![IC 8051 MCU 32K FLASH 28-QFN](/photos/12/27/122713/c8051f365-gm_sml.jpg)
C8051F365-GM
Manufacturer Part Number
C8051F365-GM
Description
IC 8051 MCU 32K FLASH 28-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Specifications of C8051F365-GM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
28-QFN
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
Package
28QFN
Device Core
8051
Family Name
C8051F36x
Maximum Speed
100 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1647
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F365-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
- Current page: 267 of 288
- Download datasheet (3Mb)
22.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 counter/
timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic ‘1’ and an interrupt request is generated if CCF interrupts are enabled. The
CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine,
and must be cleared by software. If both CAPPn and CAPNn bits are set to logic ‘1’, then the state of the
Port pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge
caused the capture.
Note: The signal at CEXn must be high or low for at least 2 system clock cycles to be recognized by the
hardware.
PWM16 ECOM CAPP CAPN MAT
Port I/O
X
X
X
X
X
X
0
1
Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
X = Don’t Care
X
X
X
1
1
1
1
1
Crossbar
1
0
1
0
0
0
0
0
Figure 22.4. PCA Capture Mode Diagram
CEXn
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
TOG
0
0
0
0
1
1
0
0
W
P
M
1
6
n
PCA0CPMn
C
O
M
E
n
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
C
A
P
P
n
PWM ECCF
C
A
P
N
n
0
1
0
0
0
0
0
1
1
1
M
A
T
n
O
G
T
n
W
P
M
n
C
C
E
F
n
0
1
X
X
X
X
X
X
0
0
C
F
C
R
Capture triggered by negative edge on
PCA0CN
Capture triggered by positive edge on
C
C
F
5
Capture triggered by transition on
C
C
F
4
PCA
Timebase
C
C
F
3
16-Bit Pulse Width Modulator
8-Bit Pulse Width Modulator
C
C
F
2
C
C
F
1
PCA Interrupt
C
C
F
0
High Speed Output
Frequency Output
Operation Mode
Capture
Software Timer
PCA0CPLn
PCA0L
CEXn
CEXn
CEXn
PCA0CPHn
PCA0H
267
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