C8051F365-GM Silicon Laboratories Inc, C8051F365-GM Datasheet - Page 93

• Manufacturer Part Number: C8051F365-GM
• Description: IC 8051 MCU 32K FLASH 28-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F365-GM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 28-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• Package: 28QFN
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 100 MHz
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1647

C8051F360/1/2/3/4/5/6/7/8/9
On the execution of the RETI instruction in the ADC0 Window Comparator ISR, the value in SFRPAGE
register is overwritten with the contents of SFRNEXT. The CIP-51 may now access the OSCICN SFR bits
as it did prior to the interrupts occurring. See Figure 9.8 below.
SFR Page 0x00
Automatically
popped off of the
stack on return from
interrupt
0x0F
SFRPAGE
(OSCICN)
SFRNEXT
popped to
SFRPAGE
SFRNEXT
SFRLAST
Figure 9.8. SFR Page Stack Upon Return From ADC2 Window Interrupt
Note that in the above example, all three bytes in the SFR Page Stack are accessible via the SFRPAGE,
SFRNEXT, and SFRLAST special function registers. If the stack is altered while servicing an interrupt, it is
possible to return to a different SFR Page upon interrupt exit than selected prior to the interrupt call. Direct
access to the SFR Page stack can be useful to enable real-time operating systems to control and manage
context switching between multiple tasks.
Push operations on the SFR Page Stack only occur on interrupt service, and pop operations only occur on
interrupt exit (execution on the RETI instruction). The automatic switching of the SFRPAGE and operation
of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic
Page Enable Bit (SFRPGEN) in the SFR Page Control Register (SFR0CN). See SFR Definition 9.1.
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