C8051F365-GM Silicon Laboratories Inc, C8051F365-GM Datasheet - Page 47
![IC 8051 MCU 32K FLASH 28-QFN](/photos/12/27/122713/c8051f365-gm_sml.jpg)
C8051F365-GM
Manufacturer Part Number
C8051F365-GM
Description
IC 8051 MCU 32K FLASH 28-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Specifications of C8051F365-GM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
28-QFN
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
Package
28QFN
Device Core
8051
Family Name
C8051F36x
Maximum Speed
100 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1647
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F365-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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5.
The ADC0 subsystem for the C8051F360/1/2/6/7/8/9 consists of two analog multiplexers (referred to col-
lectively as AMUX0) with 23 total input selections, and a 200 ksps, 10-bit successive-approximation-regis-
ter ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion
modes, and window detector are all configurable under software control via the Special Function Registers
shown in Figure 5.1. ADC0 operates in both Single-ended and Differential modes, and may be configured
to measure P1.0-P3.4 (where available), the Temperature Sensor output, or V
P3.4, VREF, or GND. The ADC0 subsystem is enabled only when the AD0EN bit in the ADC0 Control reg-
ister (ADC0CN) is set to logic ‘1’. The ADC0 subsystem is in low power shutdown when this bit is logic ‘0’.
P3.1-3.4 available on
P3.1-3.4 available on
P1.0-1.3 available on
C8051F361/2/6/7/8/9
P1.0-1.3 available on
C8051F361/2/6/7/8/9
C8051F360/1/6/8
C8051F360/1/6/8
10-Bit ADC (ADC0, C8051F360/1/2/6/7/8/9)
Sensor
Temp
VREF
GND
VDD
P1.0
P1.7
P2.0
P2.7
P3.0
P3.4
P1.0
P1.7
P2.0
P2.7
P3.0
P3.4
Figure 5.1. ADC0 Functional Block Diagram
23-to-1
23-to-1
AMUX
AMUX
AMX0P
AMX0N
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
(+)
(-)
ADC0CF
ADC
10-Bit
VDD
SAR
ADC0GTH ADC0GTL
ADC0LTH
ADC0CN
ADC0LTL
DD
Conversion
Start
with respect to P1.0-
000
001
010
011
100
101
32
AD0WINT
Compare
Window
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Timer 3 Overflow
Logic
47
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