C8051F365-GM Silicon Laboratories Inc, C8051F365-GM Datasheet - Page 185
![IC 8051 MCU 32K FLASH 28-QFN](/photos/12/27/122713/c8051f365-gm_sml.jpg)
C8051F365-GM
Manufacturer Part Number
C8051F365-GM
Description
IC 8051 MCU 32K FLASH 28-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Specifications of C8051F365-GM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
28-QFN
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
Package
28QFN
Device Core
8051
Family Name
C8051F36x
Maximum Speed
100 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1647
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F365-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
- Current page: 185 of 288
- Download datasheet (3Mb)
17.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 17.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which will be assigned to specific port pins (P0.1 and P0.2 in the
C8051F360/3 devices, P0.4 and P0.5 in the C8051F361/2/4/5/6/7/8/9 devices). If a Port pin is assigned,
the Crossbar skips that pin when assigning the next selected resource. Additionally, the Crossbar will skip
Port pins whose associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to
skip Port pins that are to be used for analog input, dedicated functions, or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to the port pins associated with the
external oscillator, V
Crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin.
Figure 17.3 shows the Crossbar Decoder priority with no Port pins skipped (P0SKIP, P1SKIP, P2SKIP,
P3SKIP = 0x00); Figure 17.4 shows the Crossbar Decoder priority with the P1.0 and P1.1 pins skipped
(P1SKIP = 0x03).
TX0
RX0
SDA
SCL
(32- and 28-
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS*
CP0
CP0A
CP1
CP1A
/SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
SF Signals
SF Signals
(48-pin)
Figure 17.3. Crossbar Priority Decoder with No Pins Skipped
pin)
REF
0
0
1
0
, external CNVSTR signal, IDA0, and any selected ADC or comparator inputs. The
2
0
P0SKIP[0:7]
3
0
P0
4
0
5
0
6
0
7
0
0
0
1
0
2
0
P1SKIP[0:7]
3
0
P1
C8051F360/1/2/3/4/5/6/7/8/9
4
0
Rev. 1.0
5
0
6
0
7
0
(32-pin and 28-pin packages)
(48-pin package)
(*4-Wire SPI Only)
0
0
1
0
2
0
P2SKIP[0:7]
3
0
P2
4
0
5
0
6
0
7
0
0
0
32/48-pin only
available on
1
0
P3.1-P3.4
2
0
P3SKIP[0:7]
3
0
P3
4
0
available
P3.5-P3.7
on 48-pin
5
0
only
6
0
7
0
185
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