C8051F365-GM Silicon Laboratories Inc, C8051F365-GM Datasheet - Page 36
![IC 8051 MCU 32K FLASH 28-QFN](/photos/12/27/122713/c8051f365-gm_sml.jpg)
C8051F365-GM
Manufacturer Part Number
C8051F365-GM
Description
IC 8051 MCU 32K FLASH 28-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Specifications of C8051F365-GM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
28-QFN
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
Package
28QFN
Device Core
8051
Family Name
C8051F36x
Maximum Speed
100 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1647
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F365-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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C8051F360/1/2/3/4/5/6/7/8/9
4.
36
AGND
Name
C2CK
GND 18, 30, 42
RST/
P4.6/
P3.0/
C2D
C2D
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
AV+
V
DD
Pinout and Package Definitions
19, 31, 43
(48-pin)
‘F360/3
Pin
48
47
46
—
6
7
8
9
5
4
3
2
1
‘F361/4/6/8
(32-pin)
Pin
32
31
30
29
28
27
—
—
—
4
3
5
6
2
1
Table 4.1. Pin Definitions for the C8051F36x
‘F362/5/7/9
(28-pin)
Pin
28
27
26
25
24
23
—
—
—
4
3
5
6
2
1
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O or
D I/O
D I/O
D I/O
D I/O
Type
A In
A In
A In
A In
A In
A In
A In
A In
A In
A In
Rev. 1.0
Power Supply Voltage.
Ground.
Analog Ground.
Analog Supply Voltage. Must be tied to +2.7 to
+3.6 V.
Device Reset. Open-drain output of internal POR or
V
reset by driving this pin low for at least 10 µs.
Clock signal for the C2 Debug Interface.
Port 4.6. See Section 17 for a complete description.
Bi-directional data signal for the C2 Debug Interface.
Port 3.0. See Section 17 for a complete description.
Bi-directional data signal for the C2 Debug Interface.
Port 0.0. See Section 17 for a complete description.
Port 0.1. See Section 17 for a complete description.
Port 0.2. See Section 17 for a complete description.
Port 0.3. See Section 17 for a complete description.
Port 0.4. See Section 17 for a complete description.
Port 0.5. See Section 17 for a complete description.
Port 0.6. See Section 17 for a complete description.
Port 0.7. See Section 17 for a complete description.
DD
Monitor. An external source can initiate a system
Description
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