C8051F365-GM Silicon Laboratories Inc, C8051F365-GM Datasheet - Page 188
![IC 8051 MCU 32K FLASH 28-QFN](/photos/12/27/122713/c8051f365-gm_sml.jpg)
C8051F365-GM
Manufacturer Part Number
C8051F365-GM
Description
IC 8051 MCU 32K FLASH 28-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Specifications of C8051F365-GM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
28-QFN
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
Package
28QFN
Device Core
8051
Family Name
C8051F36x
Maximum Speed
100 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1647
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F365-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
- Current page: 188 of 288
- Download datasheet (3Mb)
C8051F360/1/2/3/4/5/6/7/8/9
188
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
SFR Page:
SFR Address:
CP1AE
R/W
Bit7
CP1AE: Comparator1 Asynchronous Output Enable
0: Asynchronous CP1 unavailable at Port pin.
1: Asynchronous CP1 routed to Port pin.
CP1E: Comparator1 Output Enable
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
CP0AE: Comparator0 Asynchronous Output Enable
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
CP0E: Comparator0 Output Enable
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SYSCKE: /SYSCLK Output Enable
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK (divided by 1, 2, 4, or 8) routed to Port pin. The divide factor is determined by
the CLKDIV1–0 bits in register CLKSEL (See Section Section “16. Oscillators” on
page 169).
SMB0E: SMBus I/O Enable
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
SPI0E: SPI I/O Enable
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins.
URT0E: UART I/O Output Enable
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.1 and P0.2 (C8051F360/3) or P0.4 and P0.5
F
0xE1
(C8051F361/2/4/5/6/7/8/9).
CP1E
SFR Definition 17.1. XBR0: Port I/O Crossbar Register 0
R/W
Bit6
CP0AE
R/W
Bit5
CP0E
R/W
Bit4
SYSCKE
Rev. 1.0
R/W
Bit3
SMB0E
R/W
Bit2
SPI0E
R/W
Bit1
URT0E
R/W
Bit0
00000000
Reset Value
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