C8051F365-GM Silicon Laboratories Inc, C8051F365-GM Datasheet - Page 147
![IC 8051 MCU 32K FLASH 28-QFN](/photos/12/27/122713/c8051f365-gm_sml.jpg)
C8051F365-GM
Manufacturer Part Number
C8051F365-GM
Description
IC 8051 MCU 32K FLASH 28-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F36xr
Specifications of C8051F365-GM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
28-QFN
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F360DK
Minimum Operating Temperature
- 40 C
Package
28QFN
Device Core
8051
Family Name
C8051F36x
Maximum Speed
100 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1647
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F365-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
- Current page: 147 of 288
- Download datasheet (3Mb)
C8051F360/1/2/3/4/5/6/7/8/9
Certain types of instruction data or certain blocks of code can also be excluded from caching. The destina-
tions of RETI instructions are, by default, excluded from caching. To enable caching of RETI destinations,
the CHRETI bit (CCH0CN.3) can be set to ‘1’. It is generally not beneficial to cache RETI destinations
unless the same instruction is likely to be interrupted repeatedly (such as a code loop that is waiting for an
interrupt to happen). Instructions that are part of an interrupt service routine (ISR) can also be excluded
from caching. By default, ISR instructions are cached, but this can be disabled by clearing the CHISR bit
(CCH0CN.2) to ‘0’. The other information that can be explicitly excluded from caching are the data
returned by MOVC instructions. Clearing the CHMOV bit (CCH0CN.1) to ‘0’ will disable caching of MOVC
data. If MOVC caching is allowed, it can be restricted to only use slot 0 for the MOVC information (exclud-
ing cache push operations). The CHFIXM bit (CCH0TN.2) controls this behavior.
Further cache control can be implemented by disabling all cache writes. Cache writes can be disabled by
clearing the CHWREN bit (CCH0CN.7) to ‘0’. Although normal cache writes (such as those after a cache
miss) are disabled, data can still be written to the cache with a cache push operation. Disabling cache
writes can be used to prevent a non-critical section of code from changing the cache contents. Note that
regardless of the value of CHWREN, a Flash write or erase operation automatically removes the affected
bytes from the cache. Cache reads and the prefetch engine can also be individually disabled. Disabling
cache reads forces all instructions data to execute from Flash memory or from the prefetch engine. To dis-
able cache reads, the CHRDEN bit (CCH0CN.6) can be cleared to ‘0’. Note that when cache reads are dis-
abled, cache writes will still occur (if CHWREN is set to ‘1’). Disabling the prefetch engine is accomplished
using the CHPFEN bit (CCH0CN.5). When this bit is cleared to ‘0’, the prefetch engine will be disabled. If
both CHPFEN and CHRDEN are ‘0’, code will execute at a fixed rate, as instructions become available
from the Flash memory.
Cache locations can also be pre-loaded and locked with time-critical branch destinations. For example, in
a system with an ISR that must respond as fast as possible, the entry point for the ISR can be locked into
a cache location to minimize the response latency of the ISR. Up to 30 locations can be locked into the
cache at one time. Instructions are locked into cache by enabling cache push operations with the CHPUSH
bit (CCH0LC.7). When CHPUSH is set to ‘1’, a MOVC instruction will cause the four-byte segment contain-
ing the data byte to be written to the cache slot location indicated by CHSLOT (CCH0LC.4-0). CHSLOT is
them decremented to point to the next lockable cache location. This process is called a cache push opera-
tion. Cache locations that are above CHSLOT are “locked”, and cannot be changed by the processor core,
as shown in Figure 14.3. Cache locations can be unlocked by using a cache pop operation. A cache pop is
performed by writing a ‘1’ to the CHPOP bit (CCH0LC.6). When a cache pop is initiated, the value of
CHSLOT is incremented. This unlocks the most recently locked cache location, but does not remove the
information from the cache. Note that a cache pop should not be initiated if CHSLOT is equal to 11110b.
Doing so may have an adverse effect on cache performance. Important: Although locking cache loca-
tion 1 is not explicitly disabled by hardware, the entire cache will be unlocked when CHSLOT is
equal to 00000b. Therefore, cache locations 1 and 0 must remain unlocked at all times.
Rev. 1.0
147
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