DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 865

• Manufacturer Part Number: DF2378BVFQ35WV
• Description: IC H8S/2378 MCU FLASH 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• For Use With: EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

No
No
No
Write transmit data in ICDRT
Write transmit data in ICDRT
No
No
No
Read ACKBR in ICIER
Set MST = 1 and TRS
Read BBSY in ICCRB
Set MST = 1 and TRS
Read TDRE in ICSR
Read TEND in ICSR
Clear TEND in ICSR
Clear STOP in ICSR
Read STOP in ICSR
Clear TDRE in ICSR
Read TEND in ICSR
Write transmit data
Write BBSY = 1
Write BBSY = 0
= 0 in ICCRA
= 1 in ICCRA.
and SCP = 0.
Figure 16.14 Sample Flowchart for Master Transmit Mode
and SCP = 0
ACKBR=0 ?
Final byte?
BBSY=0 ?
TEND=1 ?
TDRE=1 ?
TEND=1 ?
STOP=1 ?
in ICDRT
Transmit
Initialize
mode?
Start
End
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Master receive mode
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Wait for the completion of transmission for the final byte.
[11] Clear TEND flag.
[12] Clear STOP flag.
[13] Stop condition issuance.
[14] Wait for the creation of the stop condition.
[15] Set slave receive mode. Clear TDRE.
Note: * Ensure that no interrupts occur between when BBSY is cleared to 0 and start
Test the status of the SCL and SDA lines.*
Select master transmit mode.*
Start condition issuance.*
Select transmit data for the first byte (slave address + R/W),
and clear TDRE to 0.
Wait for 1 byte to be transmitted.
Test the acknowledge bit, transferred from the specified slave device.
Set transmit data for the second and subsequent data (except for the final byte),
and clear TDRE and TEND to 0.
Wait for ICDRT empty.
Set the final byte of transmit data, and clear TDRE and TEND to 0.
condition [3].
Section 16 I
Rev.7.00 Mar. 18, 2009 page 797 of 1136
2
C Bus Interface 2 (IIC2) (Option)
REJ09B0109-0700