DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 969

• Manufacturer Part Number: DF2378BVFQ35WV
• Description: IC H8S/2378 MCU FLASH 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• For Use With: EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8. The return value in the initialization program, FPFR (general register R0L) is determined.
9. All interrupts and the use of a bus master other than the CPU are prohibited.
10. FKEY must be set to H'5A and the user MAT must be prepared for programming.
11. The parameter which is required for programming is set.
⎯ Interrupts can be accepted during the execution of the initialization program. The program
The specified voltage is applied for the specified time when programming or erasing. If
interrupts occur or the bus mastership is moved to other than the CPU during this time, the
voltage for more than the specified time will be applied and flash memory may be damaged.
Therefore, interrupts, movement of bus mastership to other than the CPU (DMAC, DTC, or
BREQ), and transition to DRAM refresh cycles are prohibited.
To prohibit the interrupt, bit 7 (I) in the condition code register (CCR) of the CPU should be
set to B'1 in interrupt control mode 0 or bits 2 to 0 (I2 to I0) in the extend control register of
the CPU should be set to B'111 in interrupt control mode 2. Then interrupts other than NMI are
held and are not executed.
The NMI interrupts must be masked within the user system.
The interrupts that are held must be executed after all program processing.
When the bus mastership is moved to other than the CPU by the DMAC, DTC, or BREQ
signal or DRAM refresh cycles are entered, the error protection state is entered. Therefore,
taking bus mastership by the DMAC, DTC, or BREQ signal is prohibited.
The start address of the programming destination of the user MAT (FMPAR) is set to general
register ER1. The start address of the program data area (FMPDR) is set to general register
ER0.
⎯ Example of the FMPAR setting
⎯ Example of the FMPDR setting
storage area and stack area in the on-chip RAM and register values must not be destroyed.
FMPAR specifies the programming destination address. When an address other than one in
the user MAT area is specified, even if the programming program is executed,
programming is not executed and an error is returned to the return value parameter FPFR.
Since the unit is 128 bytes, the lower eight bits (A7 to A0) must be H'00 or H'80 as the
boundary of 128 bytes.
When the storage destination of the program data is flash memory, even if the program
execution routine is executed, programming is not executed and an error is returned to the
FPFR parameter. In this case, the program data must be transferred to the on-chip RAM
and then programming must be executed.
Section 21 Flash Memory (0.18-μm F-ZTAT Version)
Rev.7.00 Mar. 18, 2009 page 901 of 1136
REJ09B0109-0700