DF2378BVFQ35WV Renesas Electronics America, DF2378BVFQ35WV Datasheet - Page 920

• Manufacturer Part Number: DF2378BVFQ35WV
• Description: IC H8S/2378 MCU FLASH 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378BVFQ35WV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 35MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• For Use With: EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 Flash Memory (0.35-μm F-ZTAT Version)
20.7.2
When erasing flash memory, the erase/erase-verify flowchart shown in figure 20.8 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
6. If the read data is not erased, set erase mode again, and repeat the erase/erase-verify sequence
20.7.3
All interrupts, including NMI input, are disabled when flash memory is being programmed or
erased, and while the boot program is executing in boot mode. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
2. If the interrupt exception handling is started when the vector address has not been programmed
3. If an interrupt occurred during boot program execution, it would not be possible to execute the
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REJ09B0109-0700
registers (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn.
Set a value greater than (y + z + α + β) ms as the WDT overflow period.
bits are B'00. Verify data can be read in longwords from the address to which a dummy write
was performed.
as before. The maximum number of repetitions of the erase/erase-verify sequence (N) must
not be exceeded.
erasing algorithm, with the result that normal operation could not be assured.
yet or the flash memory is being programmed or erased, the vector would not be read correctly,
possibly resulting in CPU runaway.
normal boot mode sequence.
Erase/Erase-Verify
Interrupt Handling when Programming/Erasing Flash Memory