AT90PWM216-16SUR Atmel, AT90PWM216-16SUR Datasheet - Page 172

• Manufacturer Part Number: AT90PWM216-16SUR
• Description: MCU AVR 16K FLASH 16MHZ 24SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM216-16SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 24-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.26.2
16.26.3
16.26.4
16.26.5
172
AT90PWM216/316
PSC0 Interrupt Mask Register – PIM0
PSC1 Interrupt Mask Register – PIM1
PSC2 Interrupt Mask Register – PIM2
PSC0 Interrupt Flag Register – PIFR0
• Bit 2 – POMV2A2: Output Matrix Output A Ramp 2
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 2
• Bit 1 – POMV2A1: Output Matrix Output A Ramp 1
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 1
• Bit 0 – POMV2A0: Output Matrix Output A Ramp 0
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 0
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
• Bit 5 – PSEIEn : PSC n Synchro Error Interrupt Enable
When this bit is set, the PSEIn bit (if set) generate an interrupt.
• Bit 4 – PEVEnB : PSC n External Event B Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block
B generates also an interrupt.
• Bit 3 – PEVEnA : PSC n External Event A Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block
A generates also an interrupt.
• Bit 0 – PEOPEn : PSC n End Of Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.
Bit
Read/Write
Initial Value
POAC0B
R
R
R
R
7
0
7
0
7
0
7
0
-
-
-
POAC0A
R
R
R
R
6
0
6
0
6
0
6
0
-
-
-
PSEIE0
PSEIE1
PSEIE2
PSEI0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
PEVE0B
PEVE1B
PEVE2B
PEV0B
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
PEVE0A
PEVE1A
PEVE2A
PEV0A
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
PRN01
R
R
R
R
2
0
2
0
2
0
2
0
-
-
-
PRN00
R
R
R
R
1
0
1
0
1
0
1
0
-
-
-
PEOPE0
PEOPE1
PEOPE2
PEOP2
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
7710E–AVR–08/10
PIFR0
PIM0
PIM1
PIM2