AT90PWM216-16SUR Atmel, AT90PWM216-16SUR Datasheet - Page 173

• Manufacturer Part Number: AT90PWM216-16SUR
• Description: MCU AVR 16K FLASH 16MHZ 24SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM216-16SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 24-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.26.6
16.26.7
7710E–AVR–08/10
PSC1 Interrupt Flag Register – PIFR1
PSC2 Interrupt Flag Register – PIFR2
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
• Bit 7 – POACnB : PSC n Output B Activity
This bit is set by hardware each time the output PSCOUTn1 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSC output doesn’t change due to a freezen external input
signal.
• Bit 6 – POACnA : PSC n Output A Activity
This bit is set by hardware each time the output PSCOUTn0 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSC output doesn’t change due to a freezen external input
signal.
• Bit 5 – PSEIn : PSC n Synchro Error Interrupt
This bit is set by hardware when the update (or end of PSC cycle) of the PSCn configured in
auto run (PARUNn = 1) does not occur at the same time than the PSCn-1 which has generated
the input run signal. (For PSC0, PSCn-1 is PSC2).
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSC doesn’t run at the same speed or with the same phase
than the PSC master.
• Bit 4 – PEVnB : PSC n External Event B Interrupt
This bit is set by hardware when an external event which can generates a capture or a retrigger
from Retrigger/Fault block B occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVEnB bit = 0).
• Bit 3 – PEVnA : PSC n External Event A Interrupt
This bit is set by hardware when an external event which can generates a capture or a retrigger
from Retrigger/Fault block A occurs.
Must be cleared by software by writing a one to its location.
This bit can be read even if the corresponding interrupt is not enabled (PEVEnA bit = 0).
POAC1B
POAC2B
R
R
7
0
7
0
POAC1A
POAC2A
R
R
6
0
6
0
PSEI1
PSEI2
R/W
R/W
5
0
5
0
PEV1B
PEV2B
R/W
R/W
4
0
4
0
PEV1A
PEV2A
R/W
R/W
3
0
3
0
PRN11
PRN21
AT90PWM216/316
R
R
2
0
2
0
PRN10
PRN20
R
R
1
0
1
0
PEOP1
PEOP2
R/W
R/W
0
0
0
0
PIFR1
PIFR2
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