ATMEGA128A-AUR Atmel, ATMEGA128A-AUR Datasheet - Page 146

• Manufacturer Part Number: ATMEGA128A-AUR
• Description: MCU AVR 128K FLASH 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.4
16.4.1
8151H–AVR–02/11
Register Description
SFIOR - Special Function IO Register
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 16-2. Prescaler for Timer/Counter1, Timer/Counter2, and Timer/Counter3
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR0 and PSR321 bits is kept, hence keeping the corresponding
prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted
and can be configured to the same value without the risk of one of them advancing during con-
figuration. When the TSM bit is written to zero, the PSR0 and PSR321 bits are cleared by
hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
When this bit is one, the Timer/Counter3, Timer/Counter1, and Timer/Counter2 prescaler will be
reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note
Bit
Read/Write
Initial Value
T3
CS30
CS32
CS31
The synchronization logic on the input pins (
TSM
R/W
TIMER/COUNTER3 CLOCK SOURCE
0
7
0
PSR321
CK
ExtClk
clk
T3
R
6
–
0
< f
clk_I/O
T2
/2) given a 50/50% duty cycle. Since the edge detector uses
R
5
–
0
CS20
CS22
CS21
Clear
TIMER/COUNTER2 CLOCK SOURCE
0
R
4
–
0
T3/T2/T1)
10-BIT T/C PRESCALER
clk
T2
ACME
R/W
3
0
is shown in
PUD
R/W
T1
2
0
CS10
CS12
CS11
Figure
ATmega128A
PSR0
R/W
TIMER/COUNTER1 CLOCK SOURCE
1
0
0
16-1.
PSR321
clk
R/W
clk_I/O
T1
0
0
/2.5.
SFIOR
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