ATMEGA128A-AUR Atmel, ATMEGA128A-AUR Datasheet - Page 261
ATMEGA128A-AUR
Manufacturer Part Number
ATMEGA128A-AUR
Description
MCU AVR 128K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128A-AUR
Manufacturer:
ATMEL
Quantity:
3 000
Part Number:
ATMEGA128A-AUR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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24.13.2
8151H–AVR–02/11
Boundary-scan and the Two-wire Interface
Figure 24-6. General Port Pin Schematic diagram
The two Two-wire Interface pins SCL and SDA have one additional control signal in the scan-
chain; Two-wire Interface Enable – TWIEN. As shown in
a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general
scan cell as shown in
Notes:
1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan
2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to
support tnsfor digital port pins suffice for connectivity tests. The only reason for having TWIEN
in the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary-
scan.
drive contention.
See Boundary-Scan description
Pxn
for details!
Figure 24-12
PUD:
PUExn:
OCxn:
ODxn:
IDxn:
SLEEP:
IDxn
PULLUP DISABLE
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
is attached to the TWIEN signal.
PUExn
SLEEP
OCxn
ODxn
SYNCHRONIZER
D
L
WDx:
RDx:
WPx:
RRx:
RPx:
CLK
Q
Q
Figure
I/O
:
D
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
PINxn
Q
Q
24-7, the TWIEN signal enables
RESET
RESET
Q
Q
Q
Q
PORTxn
DDxn
CLR
CLR
D
D
ATmega128A
CLK
PUD
WDx
RDx
WPx
RRx
RPx
I/O
261
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