ATMEGA128A-AUR Atmel, ATMEGA128A-AUR Datasheet - Page 247

• Manufacturer Part Number: ATMEGA128A-AUR
• Description: MCU AVR 128K FLASH 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.9.2
8151H–AVR–02/11
ADCSRA - ADC Control and Status Register A
Table 23-4.
Note:
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,
write this bit to one to start the first conversion. The first conversion after ADSC has been written
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-
tion of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADFR: ADC Free Running Select
When this bit is written to one, the ADC operates in Free Running mode. In this mode, the ADC
samples and updates the data registers continuously. Writing zero to this bit will terminate Free
Running mode.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated. The ADC
Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,
ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on
ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions
are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-
rupt is activated.
Bit
Read/Write
Initial Value
MUX4:0
11010
11011
11100
11101
11110
11111
1. Can be used for offset calibration.
Single Ended
Input
1.23V (V
0V (GND)
Input Channel and Gain Selections (Continued)
ADEN
R/W
7
0
BG
)
ADSC
R/W
6
0
Positive Differential
Input
ADC2
ADC3
ADC4
ADC5
N/A
ADFR
R/W
5
0
ADIF
R/W
4
0
ADIE
R/W
3
0
Negative Differential
Input
ADC2
ADC2
ADC2
ADC2
ADPS2
R/W
2
0
ADPS1
ATmega128A
R/W
1
0
ADPS0
R/W
0
0
Gain
1x
1x
1x
1x
ADCSRA
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