ATMEGA128A-AUR Atmel, ATMEGA128A-AUR Datasheet - Page 161

• Manufacturer Part Number: ATMEGA128A-AUR
• Description: MCU AVR 128K FLASH 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.9.2
8151H–AVR–02/11
TCNT2 - Timer/Counter Register
Table 17-5
rect PWM mode.
Table 17-5.
Note:
• Bit 2:0 – CS22:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter.
Table 17-6.
If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a compare match between TCNT2 and the OCR2 Register.
Bit
Read/Write
Initial Value
COM21
CS22
0
0
0
0
1
1
1
1
0
0
1
1
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare
match is ignored, but the set or clear is done at TOP. See
156
shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase cor-
COM20
CS21
0
0
1
1
0
0
1
1
Compare Output Mode, Phase Correct PWM Mode
Clock Select Bit Description
0
1
0
1
for more details.
R/W
7
0
CS20
Description
Normal port operation, OC2 disconnected.
Reserved
Clear OC2 on compare match when up-counting. Set OC2 on compare match
when downcounting.
Set OC2 on compare match when up-counting. Clear OC2 on compare match
when downcounting.
0
1
0
1
0
1
0
1
R/W
6
0
Description
No clock source (Timer/Counter stopped)
clk
clk
clk
clk
clk
External clock source on T2 pin. Clock on falling edge
External clock source on T2 pin. Clock on rising edge
I/O
I/O
I/O
I/O
I/O
R/W
5
0
/(No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R/W
4
0
TCNT2[7:0]
R/W
3
0
R/W
“Phase Correct PWM Mode” on page
2
0
(1)
ATmega128A
R/W
1
0
R/W
0
0
TCNT2
161