ATMEGA128A-AUR Atmel, ATMEGA128A-AUR Datasheet - Page 20
ATMEGA128A-AUR
Manufacturer Part Number
ATMEGA128A-AUR
Description
MCU AVR 128K FLASH 16MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA128A-AUR
Manufacturer:
ATMEL
Quantity:
3 000
Part Number:
ATMEGA128A-AUR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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7.2.1
8151H–AVR–02/11
Data Memory Access Times
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file,
registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the 4096bytes of internal data
SRAM in the Atmel
The Register file is described in
Figure 7-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Data Memory Map
Memory Configuration A
64 I/O Registers
160 Ext I/O Reg.
®
External SRAM
Internal SRAM
Data Memory
AVR
32 Registers
(0 - 64K x 8)
(4096 x 8)
®
ATmega128A are all accessible through all these addressing modes.
“General Purpose Register File” on page
$10FF
$1100
$FFFF
$0000 - $001F
$0020 - $005F
$0060 - $00FF
$0100
CPU
Memory Configuration B
cycles as described in
64 I/O Registers
External SRAM
Internal SRAM
Data Memory
32 Registers
(0 - 64K x 8)
(4000 x 8)
ATmega128A
$0FFF
$1000
$0000 - $001F
$0020 - $005F
$0060
$FFFF
11.
Figure
7-3.
20
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