ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 1015

• Manufacturer Part Number: ATSAM3S4AA-MU
• Description: IC MCU 32BIT 256KB FLASH 48QFN
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4AA-MU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 8x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

40. Digital-to-Analog Converter Controller (DACC)
40.1
40.2
6500C–ATARM–8-Feb-11
Description
Embedded Characteristics
The Digital-to-Analog Converter Controller (DACC) offers up to 2 analog outputs, making it possible for the
digital-to-analog conversion to drive up to 2 independent analog lines.
The DACC supports 12-bit resolution. Data to be converted are sent in a common register for all channels.
External triggers or free running mode are configurable.
The DACC integrates a Sleep Mode and connects with a PDC channel. These features reduce both power
consumption and processor intervention.
The user can configure DACC timings, such as Startup Time and Refresh Period.
• Up to 2 channels 12-bit DAC
• Up to 2 mega-samples conversion rate in single channel mode
• Flexible conversion range
• Multiple trigger sources for each channel
• 2 Sample/Hold (S/H) outputs
• Built-in offset and gain calibration
• Possibility to drive output to ground
• Possibility to use as input to analog comparator or ADC (as an internal wire and without S/H
• Two PDC channels
• Power reduction mode
stage)
SAM3S Preliminary
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