ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 710

• Manufacturer Part Number: ATSAM3S4AA-MU
• Description: IC MCU 32BIT 256KB FLASH 48QFN
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4AA-MU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 8x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

33.7.8.2
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SAM3S Preliminary
SAM3S Preliminary
Baud Rate
In SPI Mode, the baudrate generator operates in the same way as in USART synchronous
mode:
some restrictions:
In SPI Master Mode:
In SPI Slave Mode:
• the external clock SCK must not be selected (USCLKS ≠ 0x3), and the bit CLKO must be set
• to obtain correct behavior of the receiver and the transmitter, the value programmed in CD
• if the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be
• the external clock (SCK) selection is forced regardless of the value of the USCLKS field in the
• to obtain correct behavior of the receiver and the transmitter, the external clock (SCK)
to “1” in the Mode Register (US_MR), in order to generate correctly the serial clock on the
SCK pin.
must be superior or equal to 6.
even to ensure a 50:50 mark/space ratio on the SCK pin, this value can be odd if the internal
clock is selected (MCK).
Mode Register (US_MR). Likewise, the value written in US_BRGR has no effect, because
the clock is provided directly by the signal on the USART SCK pin.
frequency must be at least 6 times lower than the system clock.
See “Baud Rate in Synchronous Mode or SPI Mode” on page 683.
However, there are
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11