ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 496

• Manufacturer Part Number: ATSAM3S4AA-MU
• Description: IC MCU 32BIT 256KB FLASH 48QFN
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4AA-MU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 8x10/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

28.5.13.3
28.5.13.4
496
496
Without PDC
With PDC
SAM3S Preliminary
SAM3S Preliminary
Restrictions
Programming Sequence
• Configuration fields DSIZE, ALWYS, HALFS and FRSTS in PIO_PCMR
• Frequency of PIO controller clock must be strictly superior to 2 times the frequency of the
1. Write PIO_PCIDR and PIO_PCIER
2. Write PIO_PCMR
3. Write PIO_PCMR to set the PCEN bit to 1 in order to enable the parallel capture mode
4. Wait for a data ready by polling the DRDY flag in PIO_PCISR
5. Check OVRE flag in PIO_PCISR.
6. Read the data in PIO_PCRHR
7. If new data are expected go to step 4.
8. Write PIO_PCMR to set the PCEN bit to 0 in order to disable the parallel capture mode
1. Write PIO_PCIDR and PIO_PCIER
2. Configure PDC transfer in PDC registers.
3. Write PIO_PCMR
4. Write PIO_PCMR to set PCEN bit to 1 in order to enable the parallel capture mode
5. Wait for end of transfer by waiting the interrupt corresponding the flag ENDRX in
6. Check OVRE flag in PIO_PCISR.
7. If a new buffer transfer is expected go to step 5.
8. Write PIO_PCMR to set the PCEN bit to 0 in order to disable the parallel capture mode
Capture Mode Register”
this time (PCEN = 0 in PIO_PCMR).
clock of the device which generates the parallel data.
and
capture mode interrupt mask.
ALWYS, HALFS and FRSTS in order to configure the parallel capture mode WITHOUT
enabling the parallel capture mode.
WITHOUT changing the previous configuration.
Interrupt Status Register”
WITHOUT changing the previous configuration.
and
capture mode interrupt mask.
ALWYS, HALFS and FRSTS in order to configure the parallel capture mode WITHOUT
enabling the parallel capture mode.
WITHOUT changing the previous configuration.
PIO_PCISR
WITHOUT changing the previous configuration.
“PIO Parallel Capture Interrupt Enable Register”
“PIO Parallel Capture Interrupt Enable Register”
(“PIO Parallel Capture Interrupt Status Register”
(“PIO Parallel Capture Mode Register”
(“PIO Parallel Capture Mode Register”
) can be changed ONLY if the parallel capture mode is disabled at
) or by waiting the corresponding interrupt.
(“PIO Parallel Capture Reception Holding Register”
(“PIO Parallel Capture Interrupt Disable Register”
(“PIO Parallel Capture Interrupt Disable Register”
) in order to configure the parallel
) in order to configure the parallel
) to set the fields DSIZE,
) to set the fields DSIZE,
).
(“PIO Parallel Capture
(“PIO Parallel
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
).