ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 77
![IC MCU 32BIT 256KB FLASH 48QFN](/photos/7/34/73471/48-vqfn-6_543-5130_01-4_sml.jpg)
ATSAM3S4AA-MU
Manufacturer Part Number
ATSAM3S4AA-MU
Description
IC MCU 32BIT 256KB FLASH 48QFN
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-MU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4AA-MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 77 of 1118
- Download datasheet (24Mb)
6500C–ATARM–8-Feb-11
Table 10-13. Cortex-M3 instructions (Continued)
Mnemonic
RBIT
REV
REV16
REVSH
ROR, RORS
RRX, RRXS
RSB, RSBS
SBC, SBCS
SBFX
SDIV
SEV
SMLAL
SMULL
SSAT
STM
STMDB,
STMEA
STMFD,
STMIA
STR
STRB,
STRBT
STRD
STREX
STREXB
STREXH
STRH,
STRHT
STRT
SUB, SUBS
SUB, SUBW
SVC
SXTB
SXTH
TBB
TBH
Operands
Rd, Rn
Rd, Rn
Rd, Rn
Rd, Rn
Rd, Rm, <Rs|#n>
Rd, Rm
{Rd,} Rn, Op2
{Rd,} Rn, Op2
Rd, Rn, #lsb, #width
{Rd,} Rn, Rm
-
RdLo, RdHi, Rn, Rm
RdLo, RdHi, Rn, Rm
Rd, #n, Rm {,shift #s}
Rn{!}, reglist
Rn{!}, reglist
Rn{!}, reglist
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, Rt2, [Rn, #offset]
Rd, Rt, [Rn, #offset]
Rd, Rt, [Rn]
Rd, Rt, [Rn]
Rt, [Rn, #offset]
Rt, [Rn, #offset]
{Rd,} Rn, Op2
{Rd,} Rn, #imm12
#imm
{Rd,} Rm {,ROR #n}
{Rd,} Rm {,ROR #n}
[Rn, Rm]
[Rn, Rm, LSL #1]
Brief description
Reverse Bits
Reverse byte order in a word
Reverse byte order in each halfword
Reverse byte order in bottom halfword
and sign extend
Rotate Right
Rotate Right with Extend
Reverse Subtract
Subtract with Carry
Signed Bit Field Extract
Signed Divide
Send Event
Signed Multiply with Accumulate (32 x
32 + 64), 64-bit result
Signed Multiply (32 x 32), 64-bit result
Signed Saturate
Store Multiple registers, increment after -
Store Multiple registers, decrement
before
Store Multiple registers, increment after -
Store Register word
Store Register byte
Store Register two words
Store Register Exclusive
Store Register Exclusive byte
Store Register Exclusive halfword
Store Register halfword
Store Register word
Subtract
Subtract
Supervisor Call
Sign extend a byte
Sign extend a halfword
Table Branch Byte
Table Branch Halfword
SAM3S Preliminary
Flags
-
N,Z,C
N,Z,C,V
N,Z,C,V
-
-
-
-
-
-
-
-
-
N,Z,C,V
-
-
-
-
-
-
N,Z,C
-
Q
-
-
-
-
N,Z,C,V
-
-
Page
page 117
page 117
page 117
page 117
page 110
page 110
page 105
page 105
page 127
page 122
page 146
page 121
page 121
page 123
page 97
page 97
page 97
page 92
page 92
page 92
page 100
page 100
page 100
page 92
page 92
page 105
page 105
page 147
page 128
page 128
page 135
page 135
77
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