ATSAM3S4AA-MU Atmel, ATSAM3S4AA-MU Datasheet - Page 497
![IC MCU 32BIT 256KB FLASH 48QFN](/photos/7/34/73471/48-vqfn-6_543-5130_01-4_sml.jpg)
ATSAM3S4AA-MU
Manufacturer Part Number
ATSAM3S4AA-MU
Description
IC MCU 32BIT 256KB FLASH 48QFN
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4AA-MU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4AA-MU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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- Download datasheet (24Mb)
28.5.14
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Write Protection Registers
To prevent any single software error that may corrupt PIO behavior, certain address spaces can
be write-protected by setting the WPEN bit in the
(PIO_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Pro-
tect Status Register (PIO_WPSR) is set and the field WPVSRC indicates in which register the
write access has been attempted.
The WPVS flag is reset by writing the PIO Write Protect Mode Register (PIO_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
“PIO Enable Register” on page 502
“PIO Disable Register” on page 502
“PIO Output Enable Register” on page 503
“PIO Output Disable Register” on page 504
“PIO Input Filter Enable Register” on page 505
“PIO Input Filter Disable Register” on page 505
“PIO Multi-driver Enable Register” on page 510
“PIO Multi-driver Disable Register” on page 511
“PIO Pull Up Disable Register” on page 512
“PIO Pull Up Enable Register” on page 512
“PIO Peripheral ABCD Select Register 1” on page 514
“PIO Peripheral ABCD Select Register 2” on page 515
“PIO Output Write Enable Register” on page 520
“PIO Output Write Disable Register” on page 520
“PIO Pad Pull Down Disable Register” on page 518
“PIO Pad Pull Down Status Register” on page 519
“PIO Parallel Capture Mode Register” on page 530
“PIO Write Protect Mode Register”
SAM3S Preliminary
SAM3S Preliminary
497
497
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