ST7FLITEUS5B6 STMicroelectronics, ST7FLITEUS5B6 Datasheet - Page 47

• Manufacturer Part Number: ST7FLITEUS5B6
• Description: MCU 8BIT 1KB FLASH 128KB 8-DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEUS5B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: ST7
• No. Of I/o's: 5
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: 497-6403 - BOARD EVAL 8BIT MICRO + TDE1708497-6407 - BOARD EVAL FOR VACUUM CLEANER497-5861 - EVAL BRD POWER MOSFET/8PIN MCU497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5515 - EVAL BOARD PHASE CTRL DIMMER497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: 497-5636-5

ST7LITEUS2, ST7LITEUS5
AVD Threshold Selection register (AVDTHCR)
Refer to
this register.
Application notes
The LVDRF flag is not cleared when another reset type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can not.
Table 13.
003Ah
003Eh
Address
(Hex.)
Section 6.3.4: AVD Threshold Selection register (AVDTHCR)
SICSR
reset
value
AVDTHCR
reset
value
Bit 2 LVDRF LVD reset flag
Bit 1 AVDF Voltage Detector flag
Bit 0 AVDIE Voltage Detector interrupt enable
Register
System integrity register map and reset values
label
This bit indicates that the last Reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared when read. See WDGRF flag description in
Section 10.1.6 on page 69
BYTE, the LVDRF bit value is undefined.
Note: If the selected clock source is one of the two internal ones, and if V
This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an
interrupt request is generated when the AVDF bit is set. Refer to
additional details
0: V
1: V
This bit is set and cleared by software. It enables an interrupt to be generated when
the AVDF flag is set. The pending interrupt information is automatically cleared
when software enters the AVD interrupt routine.
0: AVD interrupt disabled
1: AVD interrupt enabled
DD
DD
remains below the selected LVD threshold during less than T
typ.), the LVDRF flag cannot be set even if the device is reset by the LVD.
If the selected clock source is the external clock (CLKIN), the flag is never
set if the reset occurs during Halt mode. In run mode the flag is set only if
f
over AVD threshold
under AVD threshold
CLKIN
CK2
7
0
0
is greater than 10 MHz.
CK1
6
1
0
for more details. When the LVD is disabled by OPTION
CK0
5
1
0
4
0
0
3
0
0
LVDRF
2
0
x
for a full description of
Figure 17
AVDF
AVD1
AWU
1
0
1
Interrupts
(33us
DD
AVDIE
for
AVD2
47/136
0
0
1