ST7FLITEUS5B6 STMicroelectronics, ST7FLITEUS5B6 Datasheet - Page 70

• Manufacturer Part Number: ST7FLITEUS5B6
• Description: MCU 8BIT 1KB FLASH 128KB 8-DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEUS5B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: ST7
• No. Of I/o's: 5
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: 497-6403 - BOARD EVAL 8BIT MICRO + TDE1708497-6407 - BOARD EVAL FOR VACUUM CLEANER497-5861 - EVAL BRD POWER MOSFET/8PIN MCU497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5515 - EVAL BOARD PHASE CTRL DIMMER497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: 497-5636-5

On-chip peripherals
Table 26.
70/136
Address
(Hex.)
0C
0B
Lite Timer Input Capture register (LTICR)
Reset value: 0000 0000 (00h)
Lite timer register map and reset values
LTCSR
Reset value
LTICR
Reset value
Register label
ICR7
7
Bit 7:0 ICR[7:0] Input capture value
Bit 2 WDGRF Force Reset/ Reset Status Flag
Bit 1 WDGE Watchdog Enable
Bit 0 WDGD Watchdog Reset Delay
ICR6
This bit is used in two ways: it is set by software to force a watchdog reset. It is set
by hardware when a watchdog reset occurs and cleared by hardware or by
software. It is cleared by hardware only when an LVD reset occurs. It can be cleared
by software after a read access to the LTCSR register.
0: No watchdog reset occurred.
1: Force a watchdog reset (write), or, a watchdog reset occurred (read).
This bit is set and cleared by software.
0: Watchdog disabled
1: Watchdog enabled
This bit is set by software. It is cleared by hardware at the end of each t
0: Watchdog reset not delayed
1: Watchdog reset delayed
These bits are read by software and cleared by hardware after a reset. If the ICF bit
in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a
rising or falling edge occurs on the LTIC pin.
ICR7
ICIE
7
0
0
ICR5
ICR6
ICF
6
0
0
ICR5
ICR4
TB
5
0
0
Read only
TBIE
ICR4
4
0
0
ICR3
ICR3
TBF
3
0
0
ICR2
ST7LITEUS2, ST7LITEUS5
WDGRF
ICR2
2
x
0
ICR1
WDGE
ICR1
1
0
0
WDG
ICR0
WDGD
ICR0
0
period.
0
0
0