ST7FLITEUS5B6 STMicroelectronics, ST7FLITEUS5B6 Datasheet - Page 74

• Manufacturer Part Number: ST7FLITEUS5B6
• Description: MCU 8BIT 1KB FLASH 128KB 8-DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEUS5B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: ST7
• No. Of I/o's: 5
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: 497-6403 - BOARD EVAL 8BIT MICRO + TDE1708497-6407 - BOARD EVAL FOR VACUUM CLEANER497-5861 - EVAL BRD POWER MOSFET/8PIN MCU497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5515 - EVAL BOARD PHASE CTRL DIMMER497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: 497-5636-5

On-chip peripherals
10.2.5
10.2.6
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Interrupts
Table 28.
Register description
Timer control status register (ATCSR)
Reset value: 0000 0000 (00h)
1. The interrupt events are connected to separate interrupt vectors (see Interrupts chapter).
2. Only if CK0=1 and CK1=0
Interrupt event
They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC
register is reset (RIM instruction).
Overflow event
7
0
CMP event
Bits 7:5 Reserved, must be kept cleared.
Bits 4:3 CK[1:0] Counter Clock Selection.
Bit 2 OVF Overflow flag.
Bit 1 OVFIE Overflow interrupt enable.
Bit 0 CMPIE Compare interrupt enable.
Interrupt events
0
These bits are set and cleared by software and cleared by hardware after a reset.
They select the clock frequency of the counter (see
selection).
This bit is set by hardware and cleared by software by reading the ATCSR register.
It indicates the transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
When set, the OVF bit stays high for 1 f
clock selection) after it has been cleared by software.
This bit is read/write by software and cleared by hardware after a reset.
0: OVF interrupt disabled
1: OVF interrupt enabled
This bit is read/write by software and clear by hardware after a reset. It allows to
mask the interrupt generation when CMPF bit is set.
0: CMPF interrupt disabled
1: CMPF interrupt enabled
(1)
CMPFx
Event
OVF
flag
0
CK1
control
Enable
CMPIE
OVFIE
Read/write
bit
CK0
COUNTER
from
Wait
Exit
Yes
Yes
cycle (up to 1ms depending on the
OVF
ST7LITEUS2, ST7LITEUS5
Table 29: Counter clock
from
Halt
Exit
No
No
OVFIE
Active-halt
Yes
from
Exit
No
(2)
CMPIE
0