ST7FLITEUS5B6 STMicroelectronics, ST7FLITEUS5B6 Datasheet - Page 72

MCU 8BIT 1KB FLASH 128KB 8-DIP

ST7FLITEUS5B6

Manufacturer Part Number
ST7FLITEUS5B6
Description
MCU 8BIT 1KB FLASH 128KB 8-DIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FLITEUS5B6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Controller Family/series
ST7
No. Of I/o's
5
Ram Memory Size
128Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
497-6403 - BOARD EVAL 8BIT MICRO + TDE1708497-6407 - BOARD EVAL FOR VACUUM CLEANER497-5861 - EVAL BRD POWER MOSFET/8PIN MCU497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5515 - EVAL BOARD PHASE CTRL DIMMER497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Other names
497-5636-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLITEUS5B6
Manufacturer:
STMicroelectronics
Quantity:
8
On-chip peripherals
Note:
Note:
Caution:
72/136
PWM frequency and duty cycle
The PWM signal frequency (f
value.
f
Following the above formula, if f
register value = 4094), and the minimum value is 2 kHz (ATR register value = 0).
The maximum value of ATR is 4094 because it must be lower than the DCR value which
must be 4095 in this case.
At reset, the counter starts counting from 0.
Software must write the duty cycle value in the DCR0H and DCR0L preload registers. The
DCR0H register must be written first. See caution below.
When a upcounter overflow occurs (OVF event), the ATR value is loaded in the upcounter,
the preloaded Duty cycle value is transferred to the Duty Cycle register and the PWM0
signal is set to a high level. When the upcounter matches the DCRx value the PWM0 signals
is set to a low level. To obtain a signal on the PWM0 pin, the contents of the DCR0 register
must be greater than the contents of the ATR register.
The polarity bit can be used to invert the output signal.
The maximum available resolution for the PWM0 duty cycle is:
Resolution = 1 / (4096 - ATR)
To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum
resolution and assuming that DCR=ATR, a 0% or 100% duty cycle can be obtained by
changing the polarity.
As soon as the DCR0H is written, the compare function is disabled and will start only when
the DCR0L value is written. If the DCR0H write occurs just before the compare event, the
signal on the PWM output may not be set to a low level. In this case, the DCRx register
should be updated just after an OVF event. If the DCR and ATR values are close, then the
DCRx register should be updated just before an OVF event, in order not to miss a compare
event and to have the right signal applied on the PWM output.
Figure 34. PWM function
PWM
= f
COUNTER
AUTO-RELOAD
DUTY CYCLE
WITH OE0=1
AND OP0=0
WITH OE0=1
AND OP0=1
REGISTER
REGISTER
(DCR0)
(ATR)
4095
000
/ (4096 - ATR)
PWM
CPU
) is controlled by the counter period and the ATR register
is 8 MHz, the maximum value of f
ST7LITEUS2, ST7LITEUS5
PWM
is 4 MHz (ATR
t

Related parts for ST7FLITEUS5B6