R4F24268NVRFQV Renesas Electronics America, R4F24268NVRFQV Datasheet - Page 483
R4F24268NVRFQV
Manufacturer Part Number
R4F24268NVRFQV
Description
MCU 256KB FLASH 48K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24268NVZFQV.pdf
(1406 pages)
Specifications of R4F24268NVRFQV
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number:
R4F24268NVRFQV
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Quantity:
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H8S/2426, H8S/2426R, H8S/2424 Group
(4)
Figure 8.27 shows an example of single address mode transfer activated by the EDREQ pin low
level.
EDREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared. At the end of the single cycle, acceptance resumes and EDREQ pin low
level sampling is performed again; this sequence of operations is repeated until the end of the
transfer.
REJ09B0466-0350 Rev. 3.50
Jul 09, 2010
Figure 8.27 Example of Single Address Mode Transfer Activated by EDREQ Pin Low Level
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle is started.
[4], [7] Acceptance is resumed after completion of single cycle.
EDREQ Pin Low Level Activation Timing
φ
EDREQ
Address bus
EDACK
EXDMA control
Channel
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of φ, and request is held.
(As in [1], EDREQ pin low level is sampled at rise of φ, and request is held.)
Idle
[1]
Minimum 3 cycles
Request
Bus release
[2]
clearance period
Single
[3]
Request
single cycle
Transfer source/
EXDMA
destination
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
[5]
clearance period
Single
[6]
Request
single cycle
Transfer source/
EXDMA
Section 8 EXDMA Controller (EXDMAC)
destination
Idle
Acceptance
resumed
[7]
Bus release
Page 453 of 1372
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