DF2378RVFQ34V Renesas Electronics America, DF2378RVFQ34V Datasheet - Page 222

• Manufacturer Part Number: DF2378RVFQ34V
• Description: IC H8S MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.3.7
BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling
or disabling of the write data buffer function, and enabling or disabling of WAIT pin input.
Bit
15
14
13
12
11
Rev.7.00 Mar. 18, 2009 page 154 of 1136
REJ09B0109-0700
Bit Name
BRLE
BREQOE
—
IDLC
ICIS1
Bus Control Register (BCR)
Initial Value
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
Description
External Bus Release Enable
Enables or disables external bus release.
0: External bus release disabled
1: External bus release enabled
BREQO Pin Enable
Controls outputting the bus request signal
(BREQO) to the external bus master in the external
bus released state, when an internal bus master
performs an external address space access, or
when a refresh request is generated.
0: BREQO output disabled
1: BREQO output enabled
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
Idle Cycle State Number Select
Specifies the number of states in the idle cycle set
by ICIS2, ICIS1, and ICIS0.
0: Idle cycle comprises 1 state
1: Idle cycle comprises 2 states
Idle Cycle Insert 1
When consecutive external read cycles are
performed in different areas, an idle cycle can be
inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
BREQ, BACK, and BREQO pins can be used as
I/O ports
BREQO pin can be used as I/O port