DF2378RVFQ34V Renesas Electronics America, DF2378RVFQ34V Datasheet - Page 877

• Manufacturer Part Number: DF2378RVFQ34V
• Description: IC H8S MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.3.2
ADCSR controls A/D conversion operations.
Bit
7
6
5
4
Bit Name
ADF
ADIE
ADST
—
A/D Control/Status Register (ADCSR)
Initial Value
0
0
0
0
R/W
R/(W) *
R/W
R/W
—
Description
A/D End Flag
A status flag that indicates the end of A/D
conversion.
[Setting conditions]
•
•
[Clearing conditions]
•
•
A/D Interrupt Enable
A/D conversion end interrupt (ADI) request enabled
when 1 is set
A/D Start
Clearing this bit to 0 stops A/D conversion, and the
A/D converter enters wait state. When this bit is set
to 1 by software, TPU (trigger), TMR (trigger), or the
ADTRG pin, A/D conversion starts. This bit remains
set to 1 during A/D conversion. In single mode,
cleared to 0 automatically when conversion on the
specified channel ends. In scan mode, conversion
continues sequentially on the specified channels
until this bit is cleared to 0 by a reset, a transition to
hardware standby mode or software.
Reserved
This bit is always read as 0 and cannot be modified.
When A/D conversion ends in single mode
When A/D conversion ends on all specified
channels in scan mode
When 0 is written after reading ADF = 1
When the DTC or DMAC is activated by an ADI
interrupt and ADDR is read
Rev.7.00 Mar. 18, 2009 page 809 of 1136
Section 17 A/D Converter
REJ09B0109-0700