DF2378RVFQ34V Renesas Electronics America, DF2378RVFQ34V Datasheet - Page 287

IC H8S MCU FLASH 512K 144LQFP

DF2378RVFQ34V

Manufacturer Part Number
DF2378RVFQ34V
Description
IC H8S MCU FLASH 512K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2378RVFQ34V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2378RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 6.9
Pin
CS2
CS3
CS4
CS5
(OE)
UCAS
LCAS
A15 to A0
D15 to D0
DCTL
Synchronous DRAM Interface Pins
With
Synchronous
DRAM Setting
RAS
CAS
WE
SDRAMφ
(CKE)
DQMU
DQML
A15 to A0
D15 to D0
DCTL
Name
Row address strobe
Column address strobe
Write enable
Clock
Clock enable
Upper data mask enable Output
Lower data mask enable Output
Address pins
Data pins
Device control pin
Rev.7.00 Mar. 18, 2009 page 219 of 1136
I/O
Output
Output
Output
Output
Output
Output
I/O
Input
Section 6 Bus Controller (BSC)
Function
Row address strobe when
areas 2 to 5 are designated as
continuous synchronous
DRAM space
Column address strobe when
areas 2 to 5 are designated as
continuous synchronous
DRAM space
Write enable strobe when
areas 2 to 5 are designated as
continuous synchronous
DRAM space
Clock only for synchronous
DRAM
Clock enable signal when
areas 2 to 5 are designated as
continuous synchronous
DRAM space
Upper data mask enable for
16-bit continuous synchronous
DRAM space access/data
mask enable for 8-bit
continuous synchronous
DRAM space access
Lower data mask enable
signal for 16-bit continuous
synchronous DRAM space
access
Row address/column address
multiplexed output pins
Data input/output pins
Output enable pin for SDRAMφ
REJ09B0109-0700

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