DF2378RVFQ34V Renesas Electronics America, DF2378RVFQ34V Datasheet - Page 750

• Manufacturer Part Number: DF2378RVFQ34V
• Description: IC H8S MCU FLASH 512K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2378RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK2378 - DEV EVAL KIT FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Watchdog Timer (WDT)
14.4
14.4.1
To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1.
If TCNT overflows without being rewritten because of a system crash or other error, the
WDTOVF signal is output.
This ensures that TCNT does not overflow while the system is operating normally. Software must
prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before
overflow occurs. This WDTOVF signal can be used to reset the chip internally in watchdog timer
mode.
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets this LSI
internally is generated at the same time as the WDTOVF signal. If a reset caused by a signal input
to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset
has priority and the WOVF bit in RSTCSR is cleared to 0.
The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0.
The internal reset signal is output for 518 states.
When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT
overflows when 1 is set in the RSTE bit in RSTCSR, an internal reset signal is generated to the
entire chip.
Rev.7.00 Mar. 18, 2009 page 682 of 1136
REJ09B0109-0700
Operation
Watchdog Timer Mode