DF2170VTE33 Renesas Electronics America, DF2170VTE33 Datasheet - Page 226
DF2170VTE33
Manufacturer Part Number
DF2170VTE33
Description
MCU 3V 256K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2170BVTE33V.pdf
(572 pages)
Specifications of DF2170VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
HD64F2170VTE33
HD64F2170VTE33
HD64F2170VTE33
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2170VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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One block is transferred in response to one transfer request, and after the transfer, the bus is
released. While the bus is released, one or more CPU bus cycles are initiated.
DREQ Pin Falling Edge Activation Timing: Figure 7.20 shows an example of normal mode
transfer activated by the DREQ pin falling edge.
DREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
DMMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the DREQ pin while acceptance via the DREQ pin is possible, the
request is held within the DMAC. Then when activation is initiated within the DMAC, the request
is cleared, and DREQ pin high level sampling for edge sensing is started. If DREQ pin high level
sampling is completed by the end of the DMA write cycle, acceptance resumes after the end of the
write cycle, and DREQ pin low level sampling is performed again; this sequence of operations is
repeated until the end of the transfer.
Figure 7.21 shows an example of block transfer mode transfer activated by the DREQ pin falling
edge.
Rev. 2.00, 03/04, page 192 of 534
φ
Address bus
DMA control
Channel
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in DMAC.
[3], [6] DMA cycle start;
[4], [7] When
Figure 7.20 Example of Normal Mode Transfer Activated by DREQ Pin Falling Edge
Acceptance after transfer enabling;
(As in [1],
Idle
[1]
Minimum 3 cycles
Request
pin high level has been sampled, acceptance is resumed after completion of write cycle.
Bus release
pin low level is sampled at rise of φ, and request is held.)
[2]
pin high level sampling is started at rise of φ.
Read
[3]
Request clearance period
Transfer source
DMA read
Write
DMA write
destination
Transfer
pin low level is sampled at rise of φ, and request is held.
Idle
Acceptance
resumed
[4]
Minimum 3 cycles
Request
Bus release
[5]
Read
[6]
Request clearance period
Transfer source
DMA read
Write
DMA write Bus release
destination
Transfer
Idle
Acceptance
resumed
[7]
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